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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510
FEATURES
Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCPS) extends tuning range Two 1.6 GHz, differential clock inputs 8 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 4 independent 1.2 GHz LVPECL outputs Additive output jitter 225 fs rms 4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 2 LVDS/CMOS outputs Serial control port Space-saving 64-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
VS GND RSET CPRSET VCP PLL REF DISTRIBUTION REF REFIN REFINB N DIVIDER FUNCTION SYNCB, RESETB PDB R DIVIDER
AD9510
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CP
PLL SETTINGS
STATUS CLK2
CLK1 CLK1B PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 LVPECL /1, /2, /3... /31, /32 LVPECL /1, /2, /3... /31, /32 SCLK SDIO SDO CSB SERIAL CONTROL PORT /1, /2, /3... /31, /32 LVDS/CMOS /1, /2, /3... /31, /32 LVDS/CMOS /1, /2, /3... /31, /32 LVPECL
CLK2B LVPECL OUT0 OUT0B OUT1 OUT1B OUT2 OUT2B OUT3 OUT3B OUT4 OUT4B
APPLICATIONS
Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure
T
LVDS/CMOS
OUT5 OUT5B OUT6 OUT6B LVDS/CMOS OUT7B
05046-001
/1, /2, /3... /31, /32
T
/1, /2, /3... /31, /32
OUT7
Figure 1.
GENERAL DESCRIPTION
The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference. There are eight independent clock outputs. Four outputs are LVPECL (1.2 GHz), and four are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. Two of the LVDS/CMOS outputs feature programmable delay elements with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each full-scale setting. The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9510 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is -40C to +85C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9510 TABLE OF CONTENTS
Specifications..................................................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Phase Noise .......................................................... 9 Clock Output Additive Time Jitter........................................... 12 PLL and Distribution Phase Noise and Spurious................... 14 Serial Control Port ..................................................................... 15 FUNCTION Pin ......................................................................... 15 STATUS Pin ................................................................................ 16 Power............................................................................................ 16 Timing Diagrams............................................................................ 17 Absolute Maximum Ratings.......................................................... 18 Thermal Characteristics ............................................................ 18 ESD Caution................................................................................ 18 Pin Configuration and Function Descriptions........................... 19 Terminology .................................................................................... 21 Typical Performance Characteristics ........................................... 22 Typical Modes of Operation.......................................................... 26 PLL with External VCXO/VCO Followed by Clock Distribution................................................................................. 26 Clock Distribution Only............................................................ 26 PLL with External VCO and Band-Pass Filter Followed by Clock Distribution...................................................................... 27 Functional Description .................................................................. 29 Overall.......................................................................................... 29 PLL Section ................................................................................. 29 PLL Reference Input--REFIN .............................................. 29 VCO/VCXO Clock Input--CLK2........................................ 29 PLL Reference Divider--R .................................................... 29 VCO/VCXO Feedback Divider--N (P, A, B) ..................... 29 A and B Counters................................................................... 30 Determining Values for P, A, B, and R ................................ 30 Phase Frequency Detector (PFD) and Charge Pump ....... 31 Antibacklash Pulse................................................................. 31 STATUS Pin ............................................................................ 31 PLL Digital Lock Detect........................................................ 31 PLL Analog Lock Detect ....................................................... 32 Loss of Reference.................................................................... 32 FUNCTION Pin ......................................................................... 33 RESETB: 58h<6:5> = 00b (Default)..................................... 33 SYNCB: 58h<6:5> = 01b ....................................................... 33 PDB: 58h<6:5> = 11b ............................................................ 33 Distribution Section................................................................... 33 CLK1 and CLK2 Clock Inputs.................................................. 33 Dividers........................................................................................ 33 Setting the Divide Ratio ........................................................ 34 Setting the Duty Cycle........................................................... 34 Divider Phase Offset.............................................................. 38 Delay Block ................................................................................. 39 Calculating the Delay ............................................................ 39 Outputs ........................................................................................ 39 Power-Down Modes .................................................................. 40 Chip Power-Down or Sleep Mode--PDB........................... 40 PLL Power-Down................................................................... 40 Distribution Power-Down .................................................... 40 Individual Clock Output Power-Down............................... 40 Individual Circuit Block Power-Down................................ 40 Reset Modes ................................................................................ 41 Power-On Reset--Start-Up Conditions when VS is Applied ................................................................ 41 Asynchronous Reset via the FUNCTION Pin ................... 41 Soft Reset via the Serial Port................................................. 41
Rev. A | Page 2 of 60
AD9510
Single-Chip Synchronization.....................................................41 SYNCB--Hardware SYNC ....................................................41 Soft SYNC--Register 58h<2> ...............................................41 Multichip Synchronization ........................................................41 Serial Control Port ..........................................................................42 Serial Control Port Pin Descriptions........................................42 General Operation of Serial Control Port ...............................42 Framing a Communication Cycle with CSB .......................42 Communication Cycle--Instruction Plus Data..................42 Write .........................................................................................42 Read ..........................................................................................43 The Instruction Word (16 Bits).................................................43 MSB/LSB First Transfers ............................................................43 Register Map and Description.......................................................46 Summary Table............................................................................46 Register Map Description ..........................................................49 Power Supply ...................................................................................56 Power Management ....................................................................56 Applications .....................................................................................57 Using the AD9510 Outputs for ADC Clock Applications ....57 CMOS Clock Distribution.........................................................57 LVPECL Clock Distribution......................................................58 LVDS Clock Distribution...........................................................58 Power and Grounding Considerations and Power Supply Rejection.......................................................................................58 Outline Dimensions........................................................................59 Ordering Guide ...........................................................................59
REVISION HISTORY
5/05--Rev. 0 to Rev. A Changes to Features ..........................................................................1 Changes to Table 1 and Table 2 .......................................................5 Changes to Table 4 ............................................................................8 Changes to Table 5 ............................................................................9 Changes to Table 6 ..........................................................................14 Changes to Table 8 and Table 9 .....................................................15 Changes to Table 11 ........................................................................16 Changes to Table 13 ........................................................................20 Changes to Figure 7 and Figure 10 ...............................................22 Changes to Figure 19 to Figure 23 ................................................24 Changes to Figure 30 and Figure 31 .............................................26 Changes to Figure 32 ......................................................................27 Changes to Figure 33 ......................................................................28 Changes to VCO/VCXO Clock Input--CLK2 Section ..............29 Changes to A and B Counters Section .........................................30 Changes to PLL Digital Lock Detect Section ..............................31 Changes to PLL Analog Lock Detect Section..............................32 Changes to Loss of Reference Section ..........................................32 Changes to FUNCTION Pin Section ...........................................33 Changes to RESETB: 58h<6:5> = 00b (Default) Section ...........33 Changes to SYNCB: 58h<6:5> = 01b Section..............................33 Changes to CLK1 and CLK2 Clock Inputs Section....................33
Changes to Calculating the Delay Section...................................38 Changes to Soft Reset via the Serial Port Section .......................41 Changes to Multichip Synchronization Section..........................41 Changes to Serial Control Port Section .......................................42 Changes to Serial Control Port Pin Descriptions Section .........42 Changes to General Operation of Serial Control Port Section .......................................................................42 Added Framing a Communication Cycle with CSB Section ....42 Added Communication Cycle--Instruction Plus Data Section.....................................................................................42 Changes to Write Section...............................................................42 Changes to Read Section................................................................42 Changes to The Instruction Word (16 Bits) Section ..................43 Changes to Table 20 ........................................................................43 Changes to MSB/LSB First Transfers Section..............................43 Changes to Table 21 ........................................................................44 Added Figure 52; Renumbered Sequentially...............................45 Changes to Table 23 ........................................................................46 Changes to Table 24 ........................................................................49 Changes to Using the AD9510 Outputs for ADC Clock Applications .....................................................................................57 4/05--Revision 0: Initial Version
Rev. A | Page 3 of 60
AD9510 SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V 5%; VS VCPS 5.5 V, TA = 25C, RSET = 4.12 k, CPRSET = 5.1 k, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFINB Input Resistance, REFIN Input Resistance, REFINB Input Capacitance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency PFD Input Frequency PFD Input Frequency Antibacklash Pulse Width Antibacklash Pulse Width Antibacklash Pulse Width CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP Three-State Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature RF CHARACTERISTICS (CLK2) 2 Input Frequency Min 0 1.45 1.40 4.0 4.5 150 1.60 1.50 4.9 5.4 2 Typ Max 250 1.75 1.60 5.8 6.3 Unit MHz mV p-p V V k k pF MHz MHz MHz ns ns ns Test Conditions/Comments
Self-bias voltage of REFIN 1. Self-bias voltage of REFINB1. Self-biased1. Self-biased1.
100 100 45 1.3 2.9 6.0
Antibacklash pulse width 0Dh<1:0> = 00b. Antibacklash pulse width 0Dh<1:0> = 01b. Antibacklash pulse width 0Dh<1:0> = 10b. 0Dh<1:0> = 00b (this is the default setting). 0Dh<1:0> = 01b. 0Dh<1:0> = 10b. Programmable. With CPRSET = 5.1 k. VCP = VCPs/2.
4.8 0.60 2.5 2.7/10 1 2 1.5 2 1.6
mA mA % k nA % % % GHz
0.5 < VCP < VCPs - 0.5 V. 0.5 < VCP < VCPs - 0.5 V. VCP = VCPs/2 V. Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS) require a minimum divide-by-2 (see the Distribution Section). Self-biased; enables ac coupling. With 200 mV p-p signal applied. CLK2 ac-coupled; CLK2B capacitively bypassed to RF ground. Self-biased. Difference at PFD. See the VCO/VCXO Feedback Divider--N (P, A, B) section.
Input Sensitivity Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance CLK2 VS. REFIN DELAY PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) CLK2 Input Frequency for PLL
1.5 1.3
150 1.6 150
1.7 1.8
mV p-p V V mV p-p k pF ps
4.0
4.8 2 500
5.6
600 1000 1600 1600 1600 300
MHz MHz MHz MHz MHz MHz
A, B counter input frequency.
Rev. A | Page 4 of 60
AD9510
Parameter NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) Min Typ Max Unit Test Conditions/Comments The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). -172 -156 -149 -142 -218 + 10 x log (fPFD) dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
@ 50 kHz PFD Frequency @ 2 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit
PLL DIGITAL LOCK DETECT WINDOW 4 Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) To Unlock After Lock (Hysteresis)4 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns)
1 2
Approximation of the PFD/CP phase noise floor (in the flat region) inside the PLL loop bandwidth. When running closed loop this phase noise is gained up by 20 x log(N) 3. Signal available at STATUS pin when selected by 08h<5:2>. Selected by Register ODh. <5> = 1b. <5> = 0b. <5> = 0b. Selected by Register ODh. <5> = 1b. <5> = 0b. <5> = 0b.
3.5 7.5 3.5 7 15 11
ns ns ns ns ns ns
REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition. CLK2 is electrically identical to CLK1; the distribution-only input can be used as differential or single-ended input (see the Clock Inputs section). 3 Example: -218 + 10 x log(fPFD) + 20 x log(N) should give the values for the in-band noise at the VCO output. 4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK INPUTS
Table 2.
Parameter CLOCK INPUTS (CLK1, CLK2) 1 Input Frequency Input Sensitivity Input Level Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance
1 2
Min 0
Typ
Max 1.6
Unit GHz mV p-p V p-p V V mV p-p k pF
Test Conditions/Comments
150 2 23 1.5 1.3 4.0 1.6 150 4.8 2 1.7 1.8 5.6
Jitter performance can be improved with higher slew rates (greater swing). Larger swings turn on the protection diodes and can degrade jitter performance. Self-biased; enables ac coupling. With 200 mV p-p signal applied; dc coupled. CLK2 ac-coupled; CLK2B ac-bypassed to RF ground. Self-biased.
CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input. With a 50 termination, this is -12.5 dBm. 3 With a 50 termination, this is +10 dBm.
Rev. A | Page 5 of 60
AD9510
CLOCK OUTPUTS
Table 3.
Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3; Differential Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) LVDS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7; Differential Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) CMOS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7 Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) Min Typ Max Unit Test Conditions/Comments Termination = 50 to VS - 2 V Output level 3Ch (3Dh) (3Eh) (3Fh)<3:2> = 10b See Figure 21
VS - 1.22 VS - 2.10 660
VS - 0.98 VS - 1.80 810
1200 VS - 0.93 VS - 1.67 965
MHz V V mV
250 1.125
360 1.23 14
800 450 25 1.375 25 24
MHz mV mV V mV mA
Termination = 100 differential; default Output level 40h (41h) (42h) (43h)<2:1> = 01b 3.5 mA termination current See Figure 22
Output shorted to GND Single-ended measurements; B outputs: inverted, termination open With 5 pF load each output; see Figure 23 @ 1 mA load @ 1 mA load
250 VS - 0.1 0.1
MHz V V
Rev. A | Page 6 of 60
AD9510
TIMING CHARACTERISTICS
Table 4.
Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT 1 Divide = Bypass Divide = 2 - 32 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS OUT1 to OUT0 on Same Part, tSKP 2 OUT2 to OUT3 on Same Part, tSKP2 All LVPECL OUTs on Same Part, tSKP2 All LVPECL OUTs Across Multiple Parts, tSKP_AB 3 Same LVPECL OUT Across Multiple Parts, tSKP_AB3 LVDS Min Typ Max Unit Test Conditions/Comments Termination = 50 to VS - 2 V Output level 3Ch (3Dh) (3Eh) (3Fh)<3:2> = 10b 20% to 80%, measured differentially 80% to 20%, measured differentially
130 130 335 375 490 545 0.5 +30 45 130
180 180 635 695
ps ps ps ps ps/C ps ps ps ps ps
-5 15 90
+85 80 180 275 130
Output Rise Time, tRL Output Fall Time, tFL PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1 OUT4, OUT5, OUT6, OUT7 Divide = Bypass Divide = 2 - 32 Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS OUT4 to OUT7 on Same Part, tSKV2 OUT5 to OUT6 on Same Part, tSKV2 All LVDS OUTs on Same Part, tSKV2 All LVDS OUTs Across Multiple Parts, tSKV_AB3 Same LVDS OUT Across Multiple Parts, tSKV_AB3 CMOS Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1 Divide = Bypass Divide = 2 - 32 Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS All CMOS OUTs on Same Part, tSKC2 All CMOS OUTs Across Multiple Parts, tSKC_AB3 Same CMOS OUT Across Multiple Parts, tSKC_AB3 LVPECL-TO-LVDS OUT Output Skew, tSKP_V LVPECL-TO-CMOS OUT Output Skew, tSKP_C LVDS-TO-CMOS OUT Output Skew, tSKV_C
200 210
350 350
ps ps
Termination = 100 differential Output level 40h (41h) (42h) (43h)<2:1> = 01b 3.5 mA termination current 20% to 80%, measured differentially 80% to 20%, measured differentially Delay off on OUT5 and OUT6
0.99 1.04
1.33 1.38 0.9
1.59 1.64
ns ns ps/C Delay off on OUT5 and OUT6 ps ps ps ps ps ps ps ns ns ps/C Delay off on OUT5 and OUT6 ps ps ps ns ns ps Everything the same; different logic type LVPECL to LVDS on same part Everything the same; different logic type LVPECL to CMOS on same part Everything the same; different logic type LVDS to CMOS on same part B outputs are inverted; termination = open 20% to 80%; CLOAD = 3 pF 80% to 20%; CLOAD = 3 pF Delay off on OUT5 and OUT6
-85 -175 -175
+270 +155 +270 450 325 681 646 865 992 1.71 1.76
1.02 1.07
1.39 1.44 1 +145
-140
+300 650 500 1.14 1.43 506
0.74 0.88 158
0.92 1.14 353
Rev. A | Page 7 of 60
AD9510
Parameter DELAY ADJUST 4 Shortest Delay Range 5 Zero Scale Full Scale Linearity, DNL Linearity, INL Longest Delay Range5 Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature Long Delay Range, 10 ns 6 Zero Scale Full Scale Short Delay Range, 1 ns6 Zero Scale Full Scale
1 2
Min
Typ
Max
Unit
0.05 0.72
0.36 1.12 0.5 0.8 0.57 10.2 0.3 0.6
0.68 1.51
ns ns LSB LSB ns ns LSB LSB
Test Conditions/Comments OUT5 (OUT6); LVDS and CMOS 35h (39h) <5:1> 11111b 36h (3Ah) <5:1> 00000b 36h (3Ah) <5:1> 11111b
0.20 9.0
0.95 11.6
35h (39h) <5:1> 00000b 36h (3Ah) <5:1> 00000b 36h (3Ah) <5:1> 11111b
0.35 -0.14 0.51 0.67
ps/C ps/C ps/C ps/C
The measurements are for CLK1. For CLK2, add approximately 25 ps. This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 4 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 5 Incremental delay; does not include propagation delay. 6 All delays between zero scale and full scale can be estimated by linear interpolation.
Rev. A | Page 8 of 60
AD9510
CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset Min Typ Max Unit Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO Input slew rate > 1 V/ns
-125 -132 -140 -148 -153 -154
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-128 -140 -148 -155 -161 -161
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-135 -145 -158 -165 -165 -166
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-131 -142 -153 -160 -165 -165
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-125 -132 -140 -151 -157 -158
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-138 -144 -154 -163 -164 -165
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. A | Page 9 of 60
AD9510
Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset Min Typ Max Unit Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO
-100 -110 -118 -129 -135 -140 -148
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-112 -122 -132 -142 -148 -152 -155
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-108 -118 -128 -138 -145 -148 -154
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-118 -129 -136 -147 -153 -156 -158
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-108 -118 -128 -138 -145 -148 -155
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-118 -127 -137 -147
Rev. A | Page 10 of 60
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
AD9510
Parameter @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset Min Typ -154 -156 -158 Max Unit dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments
Distribution Section only; does not include PLL or external VCO/VCXO
-110 -121 -130 -140 -145 -149 -156
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-122 -132 -143 -152 -158 -160 -162
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-122 -132 -140 -150 -155 -158 -160
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-128 -136 -146 -155 -161 -162
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. A | Page 11 of 60
AD9510
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT3) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT3) = 100 MHz Divide Ratio = 4 All Other LVPECL = 100 MHz All LVDS (OUT4 to OUT7) = 100 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT3) = 100 MHz Divide Ratio = 4 All Other LVPECL = 50 MHz All LVDS (OUT4 to OUT7) = 50 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT3) = 100 MHz Divide Ratio = 4 All Other LVPECL = 50 MHz All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs Off) CLK1 = 400 MHz Any LVPECL (OUT0 to OUT3) = 100 MHz Divide Ratio = 4 All Other LVPECL = 50 MHz All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs On) LVDS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 264 fs rms Min Typ Max Unit Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO BW = 12 kHz - 20 MHz (OC-12)
40
fs rms
55
fs rms
BW = 12 kHz - 20 MHz (OC-3)
215
fs rms
Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
215
fs rms
Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
222
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
225
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
225
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
Interferer(s) Interferer(s) Distribution Section only; does not include PLL or external VCO/VCXO Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
319
fs rms
Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
Rev. A | Page 12 of 60
AD9510
Parameter CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 All Other LVDS = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 All Other LVDS = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 All Other CMOS = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 All Other CMOS = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 All Other CMOS = 50 MHz (B Outputs On) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 All Other CMOS = 50 MHz (B Outputs On) All LVPECL = 50 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 CLK1 = 400 MHz Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz All Other LVDS = 50 MHz CLK1 = 400 MHz Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz All Other CMOS = 50 MHz (B Output Off)
Rev. A | Page 13 of 60
Min
Typ 395
Max
Unit fs rms
Test Conditions/Comments Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
395
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
367
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
367
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
548
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
548
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
275
fs rms
Interferer(s) Interferer(s) Distribution Section only; does not include PLL or external VCO/VCXO Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
400
fs rms
Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
374
fs rms
Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
Interferer(s) Interferer(s)
AD9510
Parameter CLK1 = 400 MHz Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz All Other CMOS = 50 MHz (B Output On) DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay FS = 1 ns (1600 A, 1C) Fine Adj. 00000 Delay FS = 1 ns (1600 A, 1C) Fine Adj. 11111 Delay FS = 2 ns (800 A, 1C) Fine Adj. 00000 Delay FS = 2 ns (800 A, 1C) Fine Adj. 11111 Delay FS = 3 ns (800 A, 4C) Fine Adj. 00000 Delay FS = 3 ns (800 A, 4C) Fine Adj. 11111 Delay FS = 4 ns (400 A, 4C) Fine Adj. 00000 Delay FS = 4 ns (400 A, 4C) Fine Adj. 11111 Delay FS = 5 ns (200 A, 1C) Fine Adj. 00000 Delay FS = 5 ns (200 A, 1C) Fine Adj. 11111 Delay FS = 11 ns (200 A, 4C) Fine Adj. 00000 Delay FS = 11 ns (200 A, 4C) Fine Adj. 00100
1
Min
Typ 555
Max
Unit fs rms
Test Conditions/Comments Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
Interferer(s) Interferer(s) Incremental additive jitter1 0.61 0.73 0.71 1.2 0.86 1.8 1.2 2.1 1.3 2.7 2.0 2.8 ps ps ps ps ps ps ps ps ps ps ps ps
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method.
PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS
Table 7.
Parameter PHASE NOISE AND SPURIOUS VCXO = 245.76 MHz, FPFD = 1.2288 MHz; R = 25, N = 200 245.76 MHz Output Phase Noise @100 kHz Offset Spurious 61.44 MHz Output Phase Noise @100 kHz Offset Spurious Min Typ Max Unit Test Conditions/Comments Depends on VCO/VCXO selection. Measured at LVPECL clock outputs; ABP = 6 ns; ICP = 5 mA; Ref = 30.72 MHz. VCXO is Toyocom TCO-2112 245.76. Divide by 1. Dominated by VCXO phase noise. First and second harmonics of FPFD.. Below measurement floor. Divide by 4. Dominated by VCXO phase noise. First and second harmonics of FPFD.. Below measurement floor.
<-145 <-97
dBc/Hz dBc
<-155 <-97
dBc/Hz dBc
Rev. A | Page 14 of 60
AD9510
SERIAL CONTROL PORT
Table 8.
Parameter CSB, SCLK (INPUTS) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tPWH Pulse Width Low, tPWL SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CSB to SCLK Setup and Hold, tS, tH CSB Minimum Pulse Width High, tPWH Min Typ Max Unit Test Conditions/Comments CSB and SCLK have 30 k internal pull-down resistors
2.0 0.8 110 1 2 2.0 0.8 10 10 2 2.7 0.4 25 16 16 2 1 6 2 3
V V A A pF V V nA nA pF V V MHz ns ns ns ns ns ns ns
FUNCTION PIN
Table 9.
Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low Min Typ Max Unit Test Conditions/Comments The FUNCTION pin has a 30 k internal pull-down resistor. This pin should normally be held high. Do not leave NC.
2.0 0.8 110 1 2 50 1.5
V V A A pF ns High speed clock cycles High speed clock is CLK1 or CLK2, whichever is being used for distribution
Rev. A | Page 15 of 60
AD9510
STATUS PIN
Table 10.
Parameter OUTPUT CHARACTERISTICS Output Voltage High (VOH) Output Voltage Low (VOL) MAXIMUM TOGGLE RATE Min Typ Max Unit Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which the STATUS pin is not CMOS digital output. See Figure 37.
2.7 0.4 100
V V MHz
Applies when PLL mux is set to any divider or counter output, or PFD up/down pulse. Also applies in analog lock detect mode. Usually debug mode only. Beware that spurs may couple to output when this pin is toggling. On-chip capacitance; used to calculate RC time constant for analog lock detect readback. Use a pull-up resistor.
ANALOG LOCK DETECT Capacitance
3
pF
POWER
Table 11.
Parameter POWER-UP DEFAULT MODE POWER DISSIPATION Power Dissipation Min Typ 550 Max 600 1.1 Unit mW W Test Conditions/Comments Power-up default state; does not include power dissipated in output load resistors. No clock. All outputs on. Four LVPECL outputs @ 800 MHz, 4 LVDS out @ 800 MHz. Does not include power dissipated in external resistors. All outputs on. Four LVPECL outputs @ 800 MHz, 4 CMOS out@ 62 MHz (5 pF load). Does not include power dissipated in external resistors. All outputs on. Four LVPECL outputs @ 800 MHz, 4 CMOS out @ 125 MHz (5 pF load). Does not include power dissipated in external resistors. Maximum sleep is entered by setting 0Ah<1:0> = 01b and 58h<4> = 1b. This powers off the PLL BG and the distribution BG references. Does not include power dissipated in terminations. Set the FUNCTION pin for PDB operation by setting 58h<6:5> = 11b. Pull PDB low. Does not include power dissipated in terminations.
Power Dissipation
1.3
W
Power Dissipation
1.5
W
Full Sleep Power-Down
35
60
mW
Power-Down (PDB)
60
80
mW
POWER DELTA CLK1, CLK2 Power-Down Divider, DIV 2 - 32 to Bypass LVPECL Output Power-Down (PD2, PD3) LVDS Output Power-Down CMOS Output Power-Down (Static) CMOS Output Power-Down (Dynamic) CMOS Output Power-Down (Dynamic) Delay Block Bypass PLL Section Power-Down
10 23 50 80 56 115 125 20 5
15 27 65 92 70 150 165 24 15
25 33 75 110 85 190 210 60 40
mW mW mW mW mW mW mW mW mW
For each divider. For each output. Does not include dissipation in termination (PD2 only). For each output. For each output. Static (no clock). For each CMOS output, single-ended. Clocking at 62 MHz with 5 pF load. For each CMOS output, single-ended. Clocking at 125 MHz with 5 pF load. Versus delay block operation at 1 ns fs with maximum delay; output clocking at 25 MHz.
Rev. A | Page 16 of 60
AD9510 TIMING DIAGRAMS
tCLK1
CLK1
DIFFERENTIAL 80% LVDS
tPECL
20%
05046-065 05046-066
tRL
tLVDS
05046-002
tFL
tCMOS
Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode
Figure 4. LVDS Timing, Differential
DIFFERENTIAL 80% LVPECL 20%
05046-064
SINGLE-ENDED 80% CMOS 3pF LOAD 20%
tRP
tFP
tRC
tFC
Figure 3. LVPECL Timing, Differential
Figure 5. CMOS Timing, Single-Ended, 3 pF Load
Rev. A | Page 17 of 60
AD9510 ABSOLUTE MAXIMUM RATINGS
Table 12.
With Respect to GND GND VS GND GND GND GND CLK1B CLK2B GND GND GND GND GND
Parameter or Pin VS VCP VCP REFIN, REFINB RSET CPRSET CLK1, CLK1B, CLK2, CLK2B CLK1 CLK2 SCLK, SDIO, SDO, CSB OUT0, OUT1, OUT2, OUT3 OUT4, OUT5, OUT6, OUT7 FUNCTION STATUS Junction Temperature 1 Storage Temperature Lead Temperature (10 sec)
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1.2 -1.2 -0.3 -0.3 -0.3 -0.3 -0.3 -65
Max +3.6 +5.8 +5.8 VS + 0.3 VS + 0.3 VS + 0.3 VS + 0.3 +1.2 +1.2 VS + 0.3 VS + 0.3 VS + 0.3 VS + 0.3 VS + 0.3 150 +150 300
Unit V V V V V V V V V V V V V V C C C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
THERMAL CHARACTERISTICS 2
Thermal Resistance 64-Lead LFCSP JA = 24C/W
1 2
See Thermal Characteristics for JA. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 18 of 60
AD9510 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VS CPRSET GND RSET VS VS OUT0 OUT0B VS GND OUT1 OUT1B VS VS GND GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
REFIN REFINB GND VS VCP CP GND GND VS CLK2 CLK2B GND VS CLK1 CLK1B FUNCTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9510
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VS OUT4 OUT4B VS VS OUT5 OUT5B VS VS OUT6 OUT6B VS VS OUT2 OUT2B VS
STATUS SCLK SDIO SDO CSB GND VS OUT7B OUT7 VS GND OUT3B OUT3 VS VS GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 6. 64-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND.
Rev. A | Page 19 of 60
05046-003
AD9510
Table 13. Pin Function Descriptions
Pin No. 1 2 3, 7, 8, 12, 22, 27, 32, 49, 50, 55, 62 4, 9, 13, 23, 26, 30, 31, 33, 36, 37, 40, 41, 44, 45, 48, 51, 52, 56, 59, 60, 64 5 6 10 11 14 15 16 Mnemonic REFIN REFINB GND Description PLL Reference Input. Complementary PLL Reference Input. Ground.
VS
Power Supply (3.3 V) VS.
VCP CP CLK2 CLK2B CLK1 CLK1B FUNCTION
17 18 19 20 21 24 25 28 29 34 35 38 39 42 43 46 47 53 54 57 58 61 63
STATUS SCLK SDIO SDO CSB OUT7B OUT7 OUT3B OUT3 OUT2B OUT2 OUT6B OUT6 OUT5B OUT5 OUT4B OUT4 OUT1B OUT1 OUT0B OUT0 RSET CPRSET
Charge Pump Power Supply VCPS. It should be greater than or equal to VS. VCPS may be set as high as 5.5 V for VCOs requiring extended tuning range. Charge Pump Output. Clock Input Used to Connect External VCO/VCXO to Feedback Divider, N. CLK2 also drives the distribution section of the chip and may be used as a generic clock input when PLL is not used. Complementary Clock Input Used in Conjunction with CLK2. Clock Input that Drives Distribution Section of the Chip. Complementary Clock Input Used in Conjunction with CLK1. Multipurpose Input May Be Programmed as a Reset (RESETB), Sync (SYNCB), or Power-Down (PDB) Pin. This pin is internally pulled down by a 30 k resistor. If this pin is left NC, the part is in reset by default. To avoid this, connect this pin to VS with a 1 k resistor. Output Used to Monitor PLL Status and Sync Status. Serial Data Clock. Serial Data I/O. Serial Data Output. Serial Port Chip Select. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block. LVDS/CMOS Output. OUT6 includes a delay block. Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block. LVDS/CMOS Output. OUT5 includes a delay block. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Current Set Resistor to Ground. Nominal value = 4.12 k. Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 k.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND.
Rev. A | Page 20 of 60
AD9510 TERMINOLOGY
Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Since these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise It is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter It is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. A | Page 21 of 60
AD9510 TYPICAL PERFORMANCE CHARACTERISTICS
0.8 0.7 0.6 0.5 DEFAULT-3 LVPECL + 2 LVDS (DIV ON) 0.4 0.3 4 LVPECL ONLY (DIV ON) 0.2 4 LVDS ONLY (DIV ON) 4 LVPECL + 4 LVDS (DIV ON) 4 LVPECL + 4 LVDS (DIV BYPASSED)
1.3
1.2
POWER (W)
POWER (W)
1.1 3 LVPECL + 4 CMOS (DIV ON) 1.0
0.9
05046-060 05046-061
0.1 0 0 400 OUTPUT FREQUENCY (MHz) 800
0.8 0 20 40 60 80 OUTPUT FREQUENCY (MHz) 100 120
Figure 7. Power vs. Frequency--LVPECL, LVDS (PLL Off)
Figure 10. Power vs. Frequency--LVPECL, CMOS (PLL Off)
CLK1 (EVAL BOARD)
REFIN (EVAL BOARD)
3GHz
5MHz
3GHz
5GHz
05046-043
Figure 8. CLK1 Smith Chart (Evaluation Board)
Figure 11. REFIN Smith Chart (Evaluation Board)
CLK2 (EVAL BOARD)
3GHz
5MHz
Figure 9. CLK2 Smith Chart (Evaluation Board)
Rev. A | Page 22 of 60
05046-044
05046-062
AD9510
10 0 -10 -20 -30 -40 -50 -60 -70
05046-058
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 CENTER 61.44MHz 30kHz/ SPAN 300kHz
05046-059
-80 -90 CENTER 245.75MHz 30kHz/ SPAN 300kHz
Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, FOUT = 245.76 MHz, FPFD = 1.2288 MHz, R = 25, N = 200
Figure 15. Phase Noise, LVPECL, DIV 4, FVCXO = 245.76 MHz, FOUT = 61.44 MHz, FPFD = 1.2288 MHz, R = 25, N = 200
-10 -20 -30 -40 -50 -60 -70 -80
05046-063
PFD NOISE REFERRED TO PFD INPUT (dBc/Hz)
0
-135
-140
-145 -150
-155
-160 -165
-90 100 CENTER 1.5GHz 250kHz/ SPAN 2.5MHz
-170 0.1
1 10 PFD FREQUENCY (MHz)
100
Figure 13. PLL Reference Spurs: VCO 1.5 GHz, FPFD = 1 MHz
5.0 4.5
Figure 16. Phase Noise (Referred to CP Output) vs. PFD Frequency
5.0 4.5
CURRENT FROM CP PIN (mA)
3.5 PUMP DOWN 3.0 2.5 2.0 1.5 1.0
05046-041
CURRENT FROM CP PIN (mA)
4.0
4.0 3.5 PUMP DOWN 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) 4.0 4.5 5.0
05046-042
PUMP UP
PUMP UP
0.5 0 0 0.5 1.0 1.5 2.0 VOLTAGE ON CP PIN (V) 2.5 3.0
Figure 14. Charge Pump Output Characteristics @ VCPs = 3.3 V
Figure 17. Charge Pump Output Characteristics @ VCPs = 5.0 V
Rev. A | Page 23 of 60
05046-057
AD9510
1.8
DIFFERENTIAL SWING (V p-p)
1.4
1.4
1.4
1.4
1.4
05046-053
05046-056
VERT 500mV/DIV
HORIZ 500ps/DIV
1.4 100
600 1100 1600 OUTPUT FREQUENCY (MHz)
Figure 18. LVPECL Differential Output @ 800 MHz
Figure 21. LVPECL Differential Output Swing vs. Frequency
750
DIFFERENTIAL SWING (mV p-p)
700
650
600
550
05046-050
05046-054
VERT 100mV/DIV
HORIZ 500ps/DIV
500 100
300
500 700 OUTPUT FREQUENCY (MHz)
900
Figure 19. LVDS Differential Output @ 800 MHz
Figure 22. LVDS Differential Output Swing vs. Frequency
3.5 2pF 3.0 2.5
OUTPUT (VPK)
10pF 2.0 1.5 1.0 20pF
05046-055
0 0 100 200 300 400 OUTPUT FREQUENCY (MHz) 500
VERT 500mV/DIV
HORIZ 1ns/DIV
600
Figure 20. CMOS Single-Ended Output @ 250 MHz with 10 pF Load
Figure 23. CMOS Single-Ended Output Swing vs. Frequency and Load
Rev. A | Page 24 of 60
05046-047
0.5
AD9510
-110 -110
-120
-120
-130
L(f) (dBc/Hz) L(f) (dBc/Hz)
05046-051
-130
-140
-140
-150
-150
-160
-160
05046-052
-170 10
100
1k
10k 100k OFFSET (Hz)
1M
10M
-170 10
100
1k
10k 100k OFFSET (Hz)
1M
10M
Figure 24. Additive Phase Noise--LVPECL DIV 1, 245.76 MHz; Distribution Section Only
-80 -90 -100 -110
L(f) (dBc/Hz) L(f) (dBc/Hz)
Figure 27. Additive Phase Noise--LVPECL DIV1, 622.08 MHz
-80 -90 -100 -110 -120 -130 -140 -150
05046-048
-120 -130 -140 -150 -160 -170 10
-160 -170 10
100
1k
10k 100k OFFSET (Hz)
1M
10M
100
1k
10k 100k OFFSET (Hz)
1M
10M
Figure 25. Additive Phase Noise--LVDS DIV 1, 245.76 MHz
-100 -100
Figure 28. Additive Phase Noise--LVDS DIV2, 122.88 MHz
-110
-110
-120
L(f) (dBc/Hz) L(f) (dBc/Hz)
-120 -130
-130
-140
-140
-150 -160
-150 -160
05046-045
-170 10
100
1k
10k 100k OFFSET (Hz)
1M
10M
-170 10
100
1k
10k 100k OFFSET (Hz)
1M
10M
Figure 26. Additive Phase Noise--CMOS DIV 1, 245.76 MHz
Figure 29. Additive Phase Noise--CMOS DIV4, 61.44 MHz
Rev. A | Page 25 of 60
05046-046
05046-049
AD9510 TYPICAL MODES OF OPERATION
PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION
This is the most common operational mode for the AD9510. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. The loop filter is usually a passive design. A VCO or a VCXO can be used. The CLK2 input is connected internally to the feedback divider, N. The CLK2 input provides the feedback path for the PLL. If the VCO/VCXO frequency exceeds maximum frequency of the output(s) being used, an appropriate divide ratio must be set in the corresponding divider(s) in the Distribution Section. Some power can be saved by shutting off unused functions, as well as by powering down any unused clock channels (see the Register Map and Description section).
CLOCK DISTRIBUTION ONLY
It is possible to use only the distribution section whenever the PLL section is not needed. Some power can be saved by shutting the PLL block off, as well as by powering down any unused clock channels (see the Register Map and Description section). In distribution mode, both the CLK1 and CLK2 inputs are available for distribution to outputs via a low jitter multiplexer (mux).
VREF REFIN R PFD N FUNCTION CLOCK INPUT 1 CLK1 STATUS CLK2 CLOCK INPUT 2 CHARGE PUMP
AD9510
PLL REF
VREF REFERENCE INPUT REFIN R
AD9510
PLL REF
LVPECL DIVIDE
LOOP FILTER
PFD N FUNCTION CLK1 STATUS
CHARGE PUMP
LVPECL DIVIDE
CLK2
VCXO, VCO
LVPECL DIVIDE LVPECL
LVPECL DIVIDE LVPECL DIVIDE LVPECL DIVIDE LVPECL SERIAL PORT DIVIDE LVDS/CMOS DIVIDE LVDS/CMOS DIVIDE CLOCK OUTPUTS
SERIAL PORT
DIVIDE LVDS/CMOS DIVIDE LVDS/CMOS DIVIDE CLOCK OUTPUTS
T
LVDS/CMOS
DIVIDE
T
LVDS/CMOS
DIVIDE
T
LVDS/CMOS
Figure 31. Clock Distribution Mode
DIVIDE
T
LVDS/CMOS
DIVIDE
Figure 30. PLL and Clock Distribution Mode
Rev. A | Page 26 of 60
05046-010
05046-011
AD9510
PLL WITH EXTERNAL VCO AND BAND-PASS FILTER FOLLOWED BY CLOCK DISTRIBUTION
An external band-pass filter may be used to try to improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate to optimize cost by choosing a less expensive VCO combined with a moderately priced filter. Note that the BPF is shown outside of the VCO-to-N divider path, with the BP filter outputs routed to CLK1. Some power can be saved by shutting off unused functions, as well as by powering down any unused clock channels (see the Register Map and Description section).
VREF REFERENCE INPUT REFIN R
AD9510
PLL REF
PFD N FUNCTION CLK1 STATUS
CHARGE PUMP
LOOP FILTER
CLK2 VCO LVPECL DIVIDE LVPECL DIVIDE LVPECL DIVIDE LVPECL BPF
SERIAL PORT
DIVIDE LVDS/CMOS DIVIDE LVDS/CMOS DIVIDE CLOCK OUTPUTS
T
LVDS/CMOS
DIVIDE
T
LVDS/CMOS
DIVIDE
Figure 32. AD9510 with VCO and BPF Filter
Rev. A | Page 27 of 60
05046-012
AD9510
VS GND RSET CPRSET VCP PLL REF
DISTRIBUTION REF REFIN 250MHz REFINB N DIVIDER FUNCTION SYNCB, RESETB, PDB R DIVIDER
AD9510
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CP
PLL SETTINGS
STATUS CLK2
CLK1 1.6GHz CLK1B PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 LVPECL /1, /2, /3... /31, /32 LVPECL /1, /2, /3... /31, /32 SCLK SDIO SDO CSB /1, /2, /3... /31, /32 LVDS/CMOS /1, /2, /3... /31, /32 SERIAL CONTROL PORT /1, /2, /3... /31, /32 LVDS/CMOS LVPECL
CLK2B LVPECL OUT0 OUT0B OUT1 OUT1B
1.6GHz
1.2GHz LVPECL OUT2 OUT2B OUT3 OUT3B OUT4 OUT4B
T
LVDS/CMOS
OUT5 OUT5B OUT6 OUT6B LVDS/CMOS OUT7B
05046-013
800MHz LVDS 250MHz CMOS
/1, /2, /3... /31, /32
T
/1, /2, /3... /31, /32
OUT7
Figure 33. Functional Block Diagram Showing Maximum Frequencies
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AD9510 FUNCTIONAL DESCRIPTION
OVERALL
Figure 33 shows a block diagram of the AD9510. The chip combines a programmable PLL core with a configurable clock distribution system. A complete PLL requires the addition of a suitable external VCO (or VCXO) and loop filter. This PLL can lock to a reference input signal and produce an output that is related to the input frequency by the ratio defined by the programmable R and N dividers. The PLL cleans up some jitter from the external reference signal, depending on the loop bandwidth and the phase noise performance of the VCO (VCXO). The output from the VCO (VCXO) can be applied to the clock distribution section of the chip, where it can be divided by any integer value from 1 to 32. The duty cycle and relative phase of the outputs can be selected. There are four LVPECL outputs, (OUT0, OUT1, OUT2, and OUT3) and four outputs that can be either LVDS or CMOS level outputs (OUT4, OUT5, OUT6, and OUT7). Two of these outputs (OUT5 and OUT6) can also make use of a variable delay block. Alternatively, the clock distribution section can be driven directly by an external clock signal, and the PLL can be powered off. Whenever the clock distribution section is used alone, there is no clock clean-up. The jitter of the input clock signal is passed along directly to the distribution section and may dominate at the clock outputs. capacitor to a quiet ground. Figure 34 shows the equivalent circuit of REFIN.
VS 10k REFIN 150 REFINB 10k 10k 150
05046-033
12k
Figure 34. REFIN Equivalent Circuit
VCO/VCXO Clock Input--CLK2
The CLK2 differential input is used to connect an external VCO or VCXO to the PLL. Only the CLK2 input port has a connection to the PLL N divider. This input can receive up to 1.6 GHz. These inputs are internally self-biased and must be ac-coupled via capacitors. Alternatively, CLK2 may be used as an input to the distribution section. This is accomplished by setting Register 45h<0> = 0b. The default condition is for CLK1 to feed the distribution section.
CLOCK INPUT STAGE VS CLK
PLL SECTION
The AD9510 consists of a PLL section and a distribution section. If desired, the PLL section can be used separately from the distribution section. The AD9510 has a complete PLL core on-chip, requiring only an external loop filter and VCO/VCXO. This PLL is based on the ADF4106, a PLL noted for its superb low phase noise performance. The operation of the AD9510 PLL is nearly identical to that of the ADF4106, offering an advantage to those with experience with the ADF series of PLLs. Differences include the addition of differential inputs at REFIN and CLK2, a different control register architecture. Also, the prescaler has been changed to allow N as low as 1. The AD9510 PLL implements the digital lock detect feature somewhat differently than the ADF4106 does, offering improved functionality at higher PFD rates. See the Register Map Description section.
CLKB 2.5k 5k 5k
05046-016
2.5k
Figure 35. CLK1, CLK2 Equivalent Input Circuit
PLL Reference Divider--R
The REFIN/REFINB inputs are routed to reference divider, R, which is a 14-bit counter. R may be programmed to any value from 1 to 16383 (a value of 0 results in a divide by 1) via its control register (OBh<5:0>, OCh<7:0>). The output of the R divider goes to one of the phase/frequency detector inputs. The maximum allowable frequency into the phase, frequency detector (PFD) must not be exceeded. This means that the REFIN frequency divided by R must be less than the maximum allowable PFD frequency. See Figure 34.
PLL Reference Input--REFIN
The REFIN/REFINB pins can be driven by either a differential or a single-ended signal. These pins are internally self-biased so that they can be ac-coupled via capacitors. It is possible to dccouple to these inputs. If REFIN is driven single-ended, the unused side (REFINB) should be decoupled via a suitable
VCO/VCXO Feedback Divider--N (P, A, B)
The N divider is a combination of a prescaler, P, (3 bits) and two counters, A (6 bits) and B (13 bits). Although the AD9510's PLL is similar to the ADF4106, the AD9510 has a redesigned prescaler that allows lower values of N. The prescaler has both a dual modulus (DM) and a fixed divide (FD) mode. The AD9510 prescaler modes are shown in Table 14.
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AD9510
Table 14. PLL Prescaler Modes
Mode (FD = Fixed Divide DM = Dual Modulus) FD FD P = 2 DM P = 4 DM P = 8 DM P = 16 DM P = 32 DM FD
A and B Counters
Divide By 1 2 P/P + 1 = 2/3 P/P + 1 = 4/5 P/P + 1 = 8/9 P/P + 1 = 16/17 P/P + 1 = 32/33 3
Value in 0Ah<4:2> 000 001 010 011 100 101 110 111
The AD9510 B counter has a bypass mode (B = 1), which is not available on the ADF4106. The B counter bypass mode is valid only when using the prescaler in FD mode. The B counter is bypassed by writing 1 to the B counter bypass bit (0Ah<6> = 1b). The valid range of the B counter is 3 to 8191. The default after a reset is 0, which is invalid. Note that the A counter is not used when the prescaler is in FD mode. Note also that the A/B counters have their own reset bit, which is primarily intended for testing. The A and B counters can also be reset using the R, A, and B counters' shared reset bit (09h<0>).
When using the prescaler in FD mode, the A counter is not used, and the B counter may need to be bypassed. The DM prescaler modes set some upper limits on the frequency, which can be applied to CLK2. See Table 15. Table 15. Frequency Limits of Each Prescaler Mode
Mode (DM = Dual Modulus) P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM P = 32 DM CLK2 <600 MHz <1000 MHz <1600 MHz <1600 MHz <1600 MHz
Determining Values for P, A, B, and R
When operating the AD9510 in a dual-modulus mode, the input reference frequency, FREF, is related to the VCO output frequency, FVCO. FVCO = (FREF/R) x (PB + A) = FREF x N/R When operating the prescaler in fixed divide mode, the A counter is not used and the equation simplifies to FVCO = (FREF/R) x (PB) = FREF x N/R By using combinations of dual modulus and fixed divide modes, the AD9510 can achieve values of N all the way down to N = 1. Table 16 shows how a 10 MHz reference input may be locked to any integer multiple of N. Note that the same value of N may be derived in different ways, as illustrated by N = 12.
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AD9510
Table 16. P, A, B, R--Smallest Values for N
FREF 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 4 4 A X X X X X X 0 1 2 1 X 0 1 X 0 0 1 B 1 1 3 4 5 3 3 3 3 4 5 5 5 6 6 3 3 N 1 2 3 4 5 6 6 7 8 9 10 10 11 12 12 12 13 FVCO 10 20 30 40 50 60 60 70 80 90 100 100 110 120 120 120 130 Mode FD FD FD FD FD FD DM DM DM DM FD DM DM FD DM DM DM Notes P = 1, B = 1 (Bypassed) P = 2, B = 1 (Bypassed) P = 1, B = 3 P = 1, B = 4 P = 1, B = 5 P = 2, B = 3 P/P + 1 = 2/3, A = 0, B = 3 P/P + 1 = 2/3, A = 1, B = 3 P/P + 1 = 2/3, A = 2, B = 3 P/P + 1 = 2/3, A = 1, B = 4 P = 2, B = 5 P/P + 1 = 2/3, A = 0, B = 5 P/P + 1 = 2/3, A = 1, B = 5 P = 2, B = 6 P/P + 1 = 2/3, A = 0, B = 6 P/P + 1 = 4/5, A = 0, B = 3 P/P + 1 = 4/5, A = 1, B = 3
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and the N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 36 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in Register 0Dh <1:0> control the width of the pulse.
VP CHARGE PUMP HI R DIVIDER D1 Q1 U1 CLR1 PROGRAMMABLE DELAY ANTIBACKLASH PULSE WIDTH HI N DIVIDER GND
05046-014
condition and thereby reduces the potential for certain spurs that could be impressed on the VCO signal.
STATUS Pin
The output multiplexer on the AD9510 allows access to various signals and internal points on the chip at the STATUS pin. Figure 37 shows a block diagram of the STATUS pin section. The function of the STATUS pin is controlled by Register 08h<5:2>.
PLL Digital Lock Detect
The STATUS pin can display two types of PLL lock detect: digital (DLD) and analog (ALD). Whenever digital lock detect is desired, the STATUS pin provides a CMOS level signal, which can be active high or active low. The digital lock detect has one of two time windows, as selected by Register 0Dh<5>. The default (ODh<5> = 0b) requires the signal edges on the inputs to the PFD to be coincident within 9.5 ns to set the DLD true, which then must separate by at least 15 ns to give DLD = false. The other setting (ODh<5> = 1) makes these coincidence times 3.5 ns for DLD = true and 7 ns for DLD = false. The DLD may be disabled by writing 1 to Register 0Dh<6>. If the signal at REFIN goes away while DLD is true, the DLD will not necessarily indicate loss-of-lock. See the Loss of Reference section for more information.
UP
U3
CP
CLR2 DOWN D2 Q2 U2
Figure 36. PFD Simplified Schematic and Timing (In Lock)
Antibacklash Pulse
The PLL features a programmable antibacklash pulse width that is set by the value in Register 0Dh<1:0>. The default antibacklash pulse width is 1.3 ns (0Dh<1:0> = 00b) and normally should not need to be changed. The antibacklash pulse eliminates the dead zone around the phase-locked
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AD9510
OFF (LOW) (DEFAULT) DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DIGITAL LOCK DETECT (ACTIVE LOW) R DIVIDER OUTPUT ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN) A COUNTER OUTPUT PRESCALER OUTPUT (NCLK) PFD UP PULSE PFD DOWN PULSE LOSS OF REFERENCE (ACTIVE HIGH) TRI-STATE ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN) LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH) LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW) LOSS OF REFERENCE (ACTIVE LOW) SYNC DETECT VS
CONTROL FOR ANALOG LOCK DETECT MODE
STATUS PIN
GND SYNC DETECT ENABLE 58h <0>
05046-015
PLL MUX CONTROL 08h <5:2>
Figure 37. STATUS Pin Circuit CLK1 Clock Input
PLL Analog Lock Detect
An analog lock detect (ALD) signal may be selected. When ALD is selected, the signal at the STATUS pin is either an open-drain P-channel (08h<5:2> = 1100) or an open-drain N-channel (08h<5:2> = 0101b). The analog lock detect signal is true (relative to the selected mode) with brief false pulses. These false pulses get shorter as the inputs to the PFD are nearer to coincidence and longer as they are further from coincidence. To extract a usable analog lock detect signal, an external RC network is required to provide an analog filter with the appropriate RC constant to allow for the discrimination of a lock condition by an external voltage comparator. A 1 k resistor in parallel with a small capacitance usually fulfills this requirement. However, some experimentation may be required to get the desired operation. The analog lock detect function may introduce some spurious energy into the clock outputs. It is prudent to limit the use of the ALD when the best possible jitter/phase noise performance is required on the clock outputs.
The digital lock detect (DLD) block of the AD9510 requires a PLL reference signal to be present in order for the digital lock detect output to be valid. It is possible to have a digital lock detect indication (DLD = true) that remains true even after a loss-of-reference signal. For this reason, the digital lock detect signal alone cannot be relied upon if the reference has been lost. There is a way to combine the DLD and the LREF into a single signal at the STATUS pin. Set 08h<5:2> = <1101> to get a signal that is the logical OR of the loss-of-lock (inverse of DLD) and the loss-of-reference (LREF) active high. If an active low version of this same signal is desired, set 08h<5:2> = <1110>. The reference monitor is enabled only after the DLD signal has been high for the number of PFD cycles set by the value in 07h<6:5>. This delay is measured in PFD cycles. The delay ranges from 3 PFD cycles (default) to 24 PFD cycles. When the reference goes away, LREF goes true and the charge pump goes into tri-state. User intervention is required to take the part out of this state. First, 07h<2> = 0b must be written to disable the loss-ofreference circuit, taking the charge pump out of tri-state and causing LREF to go false. A second write of 07h<2> = 1 is required to re-enable the loss-of-reference circuit.
PLL LOOP LOCKS DLD GOES TRUE LREF IS FALSE WRITE 07h<2> = 0 LREF SET FALSE CHARGE PUMP COMES OUT OF TRI-STATE WRITE 07h<2> = 1 LOR ENABLED
Loss of Reference
The AD9510 PLL can warn of a loss-of-reference signal at REFIN. The loss-of-reference monitor internally sets a flag called LREF. Externally, this signal can be observed in several ways on the STATUS pin, depending on the PLL MUX control settings in Register 08h<5:2>. The LREF alone can be observed as an active high signal by setting 08h<5:2> = <1010> or as an active low signal by setting 08h<5:2> = <1111>. The loss-of-reference circuit is clocked by the signal from the VCO, which means that there must be a VCO signal present in order to detect a loss of reference.
n PFD CYCLES WITH DLD TRUE (n SET BY 07h<6:5>)
CHARGE PUMP GOES INTO TRI-STATE. LREF SET TRUE. MISSING REFERENCE DETECTED
Figure 38. Loss of Reference Sequence of Events
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05046-034
CHECK FOR PRESENCE OR REFERENCE. LREF STAYS FALSE IF REFERENCE IS DETECTED.
AD9510
FUNCTION PIN
The FUNCTION pin (16) has three functions that are selected by the value in Register 58h<6:5>. This pin is internally pulled down by a 30 k resistor. If this pin is left NC, the part is in reset by default. To avoid this, connect this pin to VS with a 1 k resistor.
DISTRIBUTION SECTION
As previously mentioned, the AD9510 is partitioned into two operational sections: PLL and distribution. The PLL Section was discussed previously. If desired, the distribution section can be used separately from the PLL section.
CLK1 AND CLK2 CLOCK INPUTS
Either CLK1 or CLK2 may be selected as the input to the distribution section. The CLK1 input can be connected to drive the distribution section only. CLK1 is selected as the source for the distribution section by setting Register 45h<0> = 1. This is the power-up default state. CLK1 and CLK2 work for inputs up to 1600 MHz. The jitter performance is improved by a higher input slew rate. The input level should be between approximately 150 mV p-p to no more than 2 V p-p. Anything greater may result in turning on the protection diodes on the input pins, which could degrade the jitter performance. See Figure 35 for the CLK1 and CLK2 equivalent input circuit. These inputs are fully differential and self-biased. The signal should be ac-coupled using capacitors. If a single-ended input must be used, this can be accommodated by ac coupling to one side of the differential input only. The other side of the input should be bypassed to a quiet ac ground by a capacitor. The unselected clock input (CLK1 or CLK2) should be powered down to eliminate any possibility of unwanted crosstalk between the selected clock input and the unselected clock input.
RESETB: 58h<6:5> = 00b (Default)
In its default mode, the FUNCTION pin acts as RESETB, which generates an asynchronous reset or hard reset when pulled low. The resulting reset writes the default values into the serial control port buffer registers as well as loading them into the chip control registers. When the RESETB signal goes high again, a synchronous sync is issued (see the SYNCB: 58h<6:5> = 01b section) and the AD9510 resumes operation according to the default values of the registers.
SYNCB: 58h<6:5> = 01b
The FUNCTION pin may be used to cause a synchronization or alignment of phase among the various clock outputs. The synchronization applies only to clock outputs that * * * are not powered down the divider is not masked (no sync = 0b) are not bypassed (bypass = 0b)
SYNCB is level and rising edge sensitive. When SYNCB is low, the set of affected outputs are held in a predetermined state, defined by each divider's start high bit. On a rising edge, the dividers begin after a predefined number of fast clock cycles (fast clock is the selected clock input, CLK1 or CLK2) as determined by the values in the divider's phase offset bits. The SYNCB application of the FUNCTION pin is always active, regardless of whether the pin is also assigned to perform reset or power-down. When the SYNCB function is selected, the FUNCTION pin does not act as either RESETB or PDB.
DIVIDERS
Each of the eight clock outputs of the AD9510 has its own divider. The divider can be bypassed to get an output at the same frequency as the input (1x). When a divider is bypassed, it is powered down to save power. All integer divide ratios from 1 to 32 may be selected. A divide ratio of 1 is selected by bypassing the divider. Each divider can be configured for divide ratio, phase, and duty cycle. The phase and duty cycle values that can be selected depend on the divide ratio that is chosen.
PDB: 58h<6:5> = 11b
The FUNCTION pin may also be programmed to work as an asynchronous full power-down, PDB. Even in this full powerdown mode, there is still some residual VS current because some on-chip references continue to operate. In PDB mode, the FUNCTION pin is active low. The chip remains in a powerdown state until PDB is returned to logic high. The chip returns to the settings programmed prior to the power-down. See the Chip Power-Down or Sleep Mode--PDB section for more details on what occurs during a PDB initiated powerdown.
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AD9510
Setting the Divide Ratio
The divide ratio is determined by the values written via the SCP to the registers that control each individual output, OUT0 to OUT7. These are the even numbered registers beginning at 48h and going through 56h. Each of these registers is divided into bits that control the number of clock cycles that the divider output stays high (high_cycles <3:0>) and the number of clock cycles that the divider output stays low (low_cycles <7:4>). Each value is 4 bits and has the range of 0 to 15. The divide ratio is set by Divide Ratio = (high_cycles + 1) + (low_cycles + 1) Example 1: Set the Divide Ratio = 2 high_cycles = 0 low_cycles = 0 Divide Ratio = (0 + 1) + (0 + 1) = 2 Example 2: Set Divide Ratio = 8 high_cycles = 3 low_cycles = 3 Divide Ratio = (3 + 1) + (3 + 1) = 8 Note that a Divide Ratio of 8 may also be obtained by setting: high_cycles = 2 low_cycles = 4 Divide Ratio = (2 + 1) + (4 + 1) = 8 Although the second set of settings produces the same divide ratio, the resulting duty cycle is not the same.
Setting the Duty Cycle
The duty cycle and the divide ratio are related. Different divide ratios have different duty cycle options. For example, if Divide Ratio = 2, the only duty cycle possible is 50%. If the Divide Ratio = 4, the duty cycle may be 25%, 50%, or 75%. The duty cycle is set by Duty Cycle = (high_cycles + 1)/((high_cycles + 1) + (low_cycles + 1)) See Table 17 for the values for the available duty cycles for each divide ratio.
Table 17. Duty Cycle and Divide Ratio
Divide Ratio 2 3 3 4 4 4 5 5 5 5 6 6 6 6 6 7 7 7 7 Duty Cycle (%) 50 67 33 50 75 25 60 40 80 20 50 67 33 83 17 57 43 71 29 48h to 56h LO <7:4> HI<3:0> 0 0 1 1 0 2 1 2 0 3 2 1 3 0 4 2 3 1 4 0 1 0 1 2 0 2 1 3 0 2 3 1 4 0 3 2 4 1 Divide Ratio 7 7 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 10 10 Duty Cycle (%) 86 14 50 63 38 75 25 88 13 56 44 67 33 78 22 89 11 50 60 48h to 56h LO <7:4> HI<3:0> 0 5 3 2 4 1 5 0 6 3 4 2 5 1 6 0 7 4 3 5 0 3 4 2 5 1 6 0 4 3 5 2 6 1 7 0 4 5
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AD9510
Divide Ratio 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 Duty Cycle (%) 40 70 30 80 20 90 10 55 45 64 36 73 27 82 18 91 9 50 58 42 67 33 75 25 83 17 92 8 54 46 62 38 69 31 77 23 85 15 92 8 50 57 43 64 36 71 29 79 21 86 14 48h to 56h LO <7:4> HI<3:0> 5 2 6 1 7 0 8 4 5 3 6 2 7 1 8 0 9 5 4 6 3 7 2 8 1 9 0 A 5 6 4 7 3 8 2 9 1 A 0 B 6 5 7 4 8 3 9 2 A 1 B 3 6 2 7 1 8 0 5 4 6 3 7 2 8 1 9 0 5 6 4 7 3 8 2 9 1 A 0 6 5 7 4 8 3 9 2 A 1 B 0 6 7 5 8 4 9 3 A 2 B 1 Divide Ratio 14 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 Duty Cycle (%) 93 7 53 47 60 40 67 33 73 27 80 20 87 13 93 7 50 56 44 63 38 69 31 75 25 81 19 88 13 94 6 53 47 59 41 65 35 71 29 76 24 82 18 88 12 94 6 50 56 44 61 48h to 56h LO <7:4> HI<3:0> 0 C 6 7 5 8 4 9 3 A 2 B 1 C 0 D 7 6 8 5 9 4 A 3 B 2 C 1 D 0 E 7 8 6 9 5 A 4 B 3 C 2 D 1 E 0 F 8 7 9 6 C 0 7 6 8 5 9 4 A 3 B 2 C 1 D 0 7 8 6 9 5 A 4 B 3 C 2 D 1 E 0 8 7 9 6 A 5 B 4 C 3 D 2 E 1 F 0 8 9 7 A
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AD9510
Divide Ratio 18 18 18 18 18 18 18 18 18 18 18 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 21 21 21 21 21 21 21 21 21 21 21 21 22 Duty Cycle (%) 39 67 33 72 28 78 22 83 17 89 11 53 47 58 42 63 37 68 32 74 26 79 21 84 16 50 55 45 60 40 65 35 70 30 75 25 80 20 52 48 57 43 62 38 67 33 71 29 76 24 50 48h to 56h LO <7:4> HI<3:0> A 5 B 4 C 3 D 2 E 1 F 8 9 7 A 6 B 5 C 4 D 3 E 2 F 9 8 A 7 B 6 C 5 D 4 E 3 F 9 A 8 B 7 C 6 D 5 E 4 F A 6 B 5 C 4 D 3 E 2 F 1 9 8 A 7 B 6 C 5 D 4 E 3 F 2 9 A 8 B 7 C 6 D 5 E 4 F 3 A 9 B 8 C 7 D 6 E 5 F 4 A Divide Ratio 22 22 22 22 22 22 22 22 22 22 23 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24 25 25 25 25 25 25 25 25 26 26 26 26 26 26 26 27 27 27 27 27 27 28 Duty Cycle (%) 55 45 59 41 64 36 68 32 73 27 52 48 57 43 61 39 65 35 70 30 50 54 46 58 42 63 38 67 33 52 48 56 44 60 40 64 36 50 54 46 58 42 62 38 52 48 56 44 59 41 50 48h to 56h LO <7:4> HI<3:0> 9 B 8 C 7 D 6 E 5 F A B 9 C 8 D 7 E 6 F B A C 9 D 8 E 7 F B C A D 9 E 8 F C B D A E 9 F C D B E A F D B 9 C 8 D 7 E 6 F 5 B A C 9 D 8 E 7 F 6 B C A D 9 E 8 F 7 C B D A E 9 F 8 C D B E A F 9 D C E B F A D
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AD9510
Divide Ratio 28 28 28 28 29 29 29 29 Duty Cycle (%) 54 46 57 43 52 48 55 45 48h to 56h LO <7:4> HI<3:0> C E B F D E C F E C F B E D F C Divide Ratio 30 30 30 31 31 32 Duty Cycle (%) 50 53 47 52 48 50 48h to 56h LO <7:4> HI<3:0> E D F E F F E F D F E F
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AD9510
Divider Phase Offset
The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers which set the phase and start high/low bit for each output. These are the odd numbered registers from 49h to 57h. Each divider has a 4-bit phase offset <3:0> and a start high or low bit <4>. Following a sync pulse, the phase offset word determines how many fast clock (CLK1 or CLK2) cycles to wait before initiating a clock output edge. The Start H/L bit determines if the divider output starts low or high. By giving each divider a different phase offset, output-to-output delays can be set in increments of the fast clock period, tCLK. Figure 39 shows four dividers, each set for DIV = 4, 50% duty cycle. By incrementing the phase offset from 0 to 3, each output is offset from the initial edge by a multiple of tCLK.
0 CLOCK INPUT CLK
DIVIDER OUTPUTS DIV = 4, DUTY = 50% START = 0, PHASE = 0 START = 0, PHASE = 1 START = 0, PHASE = 2 START = 0, PHASE = 3
Setting the phase offset to Phase = 4 results in the same relative phase as the first channel, Phase = 0 or 360. In general, by combining the 4-bit phase offset and the Start H/L bit, there are 32 possible phase offset states (see Table 18). Table 18. Phase Offset--Start H/L Bit
Phase Offset (Fast Clock Rising Edges) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 49h to 57h Phase Offset <3:0> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Start H/L <4> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
tCLK
tCLK
3 x tCLK
05046-035
2 x tCLK
Figure 39. Phase Offset--All Dividers Set for DIV = 4, Phase Set from 0 to 3
For example: CLK1 = 491.52 MHz tCLK1 = 1/491.52 = 2.0345 ns For DIV = 4 Phase Offset 0 = 0 ns Phase Offset 1 = 2.0345 ns Phase Offset 2 = 4.069 ns Phase Offset 3 = 6.104 ns The four outputs may also be described as: OUT1 = 0 OUT2 = 90 OUT3 = 180 OUT4 = 270
The resolution of the phase offset is set by the fast clock period (tCLK) at CLK1 or CLK2. As a result, every divide ratio does not have 32 unique phase offsets available. For any divide ratio, the number of unique phase offsets is numerically equal to the divide ratio (see Table 18): DIV = 4 Unique Phase Offsets Are Phase = 0, 1, 2, 3 DIV= 7
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AD9510
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6 DIV = 18 Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 Phase offsets may be related to degrees by calculating the phase step for a particular divide ratio: Phase Step = 360/(Divide Ratio) = 360/DIV Using some of the same examples, DIV = 4 Phase Step = 360/4 = 90 Unique Phase Offsets in Degrees Are Phase = 0, 90, 180, 270 DIV = 7 Phase Step = 360/7 = 51.43 Unique Phase Offsets in Degrees Are Phase = 0, 51.43, 102.86, 154.29, 205.71, 257.15, 308.57 This path adds some jitter greater than that specified for the nondelay outputs. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC, rather than for data converters. The jitter is higher for long full scales (~10 ns). This is because the delay block uses a ramp and trip points to create the variable delay. A longer ramp means more noise might be introduced.
Calculating the Delay
The following values and equations are used to calculate the delay of the delay block. Value of Ramp Current Control Bits (Register 35h or Register 39h <2:0>) = Iramp_bits IRAMP (A) = 200 x (Iramp_bits + 1) No. of Caps = No. of 0s + 1 in Ramp Control Capacitor (Register 35h or Register 39h <5:3>), that is, 101 = 1 + 1 = 2; 110 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1) Delay_Range (ns) = 200 x ((No. of Caps + 3)/(IRAMP)) x 1.3286
No.of Caps - 1 x6 Offset (ns ) = 0.34 + (1600 - I RAMP )x 10 -4 + I RAMP
DELAY BLOCK
OUT5 and OUT6 (LVDS/CMOS) include an analog delay element that can be programmed (Register 34h to Register 3Ah) to give variable time delays (t) in the clock signal passing through that output.
CLOCK INPUT
Delay_Full_Scale (ns) = Delay_Range + Offset Fine_Adj = Value of Delay Fine Adjust (Register 36h or Register 3Ah <5:1>), that is, 11111 = 31 Delay (ns) = Offset + Delay_Range x Fine_adj x (1/31)
OUTPUTS
SELECT
/N
LVDS CMOS OUTPUT DRIVER
05046-036
OUT5 OUT6 ONLY
T
FINE DELAY ADJUST (32 STEPS) FULL-SCALE: 1ns TO 10ns
The AD9510 offers three different output level choices: LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL only. OUT4 to OUT7 can be selected as either LVDS or CMOS. Each output can be enabled or turned off as needed to save power. The simplified equivalent circuit of the LVPECL outputs is shown in Figure 41.
3.3V
Figure 40. Analog Delay (OUT5 andOUT6)
The amount of delay that can be used is determined by the frequency of the clock being delayed. The amount of delay can approach one-half cycle of the clock period. For example, for a 10 MHz clock, the delay can extend to the full 10 ns maximum of which the delay element is capable. However, for a 100 MHz clock (with 50% duty cycle), the maximum delay is less than 5 ns (or half of the period). OUT5 and OUT6 allow a full-scale delay in the range 1 ns to 10 ns. The full-scale delay is selected by choosing a combination of ramp current and the number of capacitors by writing the appropriate values into Register 35h and Register 39h. There are 32 fine delay settings for each full scale, set by Register 36h and Register 3Ah.
Rev. A | Page 39 of 60
MUX
OUT OUTB
GND
Figure 41. LVPECL Output Simplified Equivalent Circuit
05046-037
AD9510
3.5mA
Table 19. Register 0Ah: PLL Power-Down
<1> 0 0 1 1 <0> 0 1 0 1 Mode Normal Operation Asynchronous Power-Down Normal Operation Synchronous Power-Down
OUT OUTB
05046-038
3.5mA
In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into power-down on the occurrence of the next charge pump event after the registers are updated.
Figure 42. LVDS Output Simplified Equivalent Circuit
POWER-DOWN MODES
Chip Power-Down or Sleep Mode--PDB
The PDB chip power-down turns off most of the functions and currents in the AD9510. When the PDB mode is enabled, a chip power-down is activated by taking the FUNCTION pin to a logic low level. The chip remains in this power-down state until PDB is brought back to logic high. When woken up, the AD9510 returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the PDB mode is active. The PDB power-down mode shuts down the currents on the chip, except the bias current necessary to maintain the LVPECL outputs in a safe shutdown mode. This is needed to protect the LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tri-stated. Because this is not a complete power-down, it can be called sleep mode. When the AD9510 is in a PDB power-down or sleep mode, the chip is in the following state: * * * * * * The PLL is off (asynchronous power-down). All clocks and sync circuits are off. All dividers are off. All LVDS/CMOS outputs are off. All LVPECL outputs are in safe off mode. The serial control port is active, and the chip responds to commands.
Distribution Power-Down
The distribution section can be powered down by writing to Register 58h<3> = 1. This turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation <00>, it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to <11>, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. When combined with the PLL power-down, this mode results in the lowest possible power-down current for the AD9510.
Individual Clock Output Power-Down
Any of the eight clock distribution outputs may be powered down individually by writing to the appropriate registers via the SCP. The register map details the individual power-down settings for each output. The LVDS/CMOS outputs may be powered down, regardless of their output load configuration. The LVPECL outputs have multiple power-down modes (see Register Address 3C, Register Address 3D, Register Address 3E, and Register Address 3F in Table 24). These give some flexibility in dealing with various output termination conditions. When the mode is set to <10>, the LVPECL output is protected from reverse bias to 2 VBE + 1 V. If the mode is set to <11>, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. This setting also affects the operation when the distribution block is powered down with Register 58h<3> = 1b (see the Distribution Power-Down section).
If the AD9510 clock outputs must be synchronized to each other, a SYNC (see the Single-Chip Synchronization section) is required upon exiting power-down mode.
Individual Circuit Block Power-Down
Many of the AD9510 circuit blocks (CLK1, CLK2, REFIN, and so on) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed.
PLL Power-Down
The PLL section of the AD9510 can be selectively powered down. There are three PLL power-down modes, set by the values in Register 0Ah<1:0>, as shown in Table 19.
Rev. A | Page 40 of 60
AD9510
RESET MODES
The AD9510 has several ways to force the chip into a reset condition. Synchronization of two or more AD9510s requires a fast clock and a slow clock. The fast clock can be up to 1 GHz and may be the clock driving the master AD9510 CLK1 input or one of the outputs of the master. The fast clock acts as the input to the distribution section of the slave AD9510 and is connected to its CLK1 input. The PLL may be used on the master, but the slave PLL is not used. The slow clock is the clock that is synchronized across the two chips. This clock must be no faster than one-fourth of the fast clock, and no greater than 250 MHz. The slow clock is taken from one of the outputs of the master AD9510 and acts as the REFIN (or CLK2) input to the slave AD9510. One of the outputs of the slave must provide this same frequency back to the CLK2 (or REFIN) input of the slave. Multichip synchronization is enabled by writing Register 58h<0> = 1 on the slave AD9510. When this bit is set, the STATUS pin becomes the output for the SYNC signal. A low signal indicates an in-sync condition, and a high indicates an out-of-sync condition. Register 58h<1> selects the number of fast clock cycles that are the maximum separation of the slow clock edges that are considered synchronized. When 58h<1> = 0 (default), the slow clock edges must be coincident within 1 to 1.5 high speed clock cycles. If the coincidence of the slow clock edges is closer than this amount, the SYNC flag stays low. If the coincidence of the slow clock edges is greater than this amount, the SYNC flag is set high. When Register 58h<1> = 1b, the amount of coincidence required is 0.5 fast clock cycles to 1 fast clock cycles. Whenever the SYNC flag is set (high) indicating an out-of-sync condition, a SYNCB signal applied simultaneously at the FUNCTION pins of both AD9510s brings the slow clocks into synchronization.
AD9510
MASTER FAST CLOCK <1GHz FUNCTION (SYNCB) SLOW CLOCK <250MHz OUTN
Power-On Reset--Start-Up Conditions when VS is Applied
A power-on reset (POR) is issued when the VS power supply is turned on. This initializes the chip to the power-on conditions that are determined by the default register settings. These are indicated in the default value column of Table 23.
Asynchronous Reset via the FUNCTION Pin
As mentioned in the FUNCTION Pin section, a hard reset, RESETB: 58h<6:5> = 00b (Default), restores the chip to the default settings.
Soft Reset via the Serial Port
The serial control port allows a soft reset by writing to Register 00h<5> = 1b. When this bit is set, the chip executes a soft reset. This restores the default values to the internal registers, except for Register 00h itself. This bit is not self-clearing. The bit must be written to 00h<5> = 0b in order for the operation of the part to continue.
SINGLE-CHIP SYNCHRONIZATION
SYNCB--Hardware SYNC
The AD9510 clocks can be synchronized to each other at any time. The outputs of the clocks are forced into a known state with respect to each other and then allowed to continue clocking from that state in synchronicity. Before a synchronization is done, the FUNCTION Pin must be set to act as the SYNCB: 58h<6:5> = 01b input (58h<6:5> = 01b). Synchronization is done by forcing the FUNCTION pin low, creating a SYNCB signal and then releasing it. See the SYNCB: 58h<6:5> = 01b section for a more detailed description of what happens when the SYNCB: 58h<6:5> = 01b signal is issued.
Soft SYNC--Register 58h<2>
A soft SYNC may be issued by means of a bit in Registers 58h<2>. This soft SYNC works the same as the SYNCB, except that the polarity is reversed. A 1 written to this bit forces the clock outputs into a known state with respect to each other. When a 0 is subsequently written to this bit, the clock outputs continue clocking from that state in synchronicity.
OUTM FSYNC
SYNCB CLK2 REFIN SLOW CLOCK <250MHz SYNC DETECT
05046-039
AD9510
SLAVE FSYNC OUTY
MULTICHIP SYNCHRONIZATION
The AD9510 provides a means of synchronizing two or more AD9510s. This is not an active synchronization; it requires user monitoring and action. The arrangement of two AD9510s to be synchronized is shown in Figure 43.
FAST CLOCK CLK1 <1GHz
FUNCTION (SYNCB)
STATUS (SYNC)
Figure 43. Multichip Synchronization
Rev. A | Page 41 of 60
AD9510 SERIAL CONTROL PORT
The AD9510 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9510 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI(R) and Intel(R) SSR(R) protocols. The serial control port allows read/write access to all registers that configure the AD9510. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9510 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/SDO). CSB stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (W1:W0 must be set to 00, 01, or 10, see Table 20). In these modes, CSB can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. CSB can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. During this period, the serial control port state machine enters a wait state until all data has been sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining transfer or by returning the CSB low for at least one complete SCLK cycle (but less than eight SCLK cycles). Raising the CSB on a nonbyte boundary terminates the serial transfer and flushes the buffer. In the streaming mode (W1:W0 = 11b), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the MSB/LSB First Transfers section). CSB must be raised at the end of the last byte to be transferred, thereby ending the stream mode.
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 k resistor to ground. SDIO (serial data input/output) is a dual-purpose pin and acts as either an input only or as both an input/output. The AD9510 defaults to two unidirectional pins for I/O, with SDIO used as an input, and SDO as an output. Alternatively, SDIO can be used as a bidirectional I/O pin by writing to the SDO enable register at 00h<7> = 1b. SDO (serial data out) is used only in the unidirectional I/O mode (00h<7> = 0, default) as a separate output pin for reading back data. The AD9510 defaults to this I/O mode. Bidirectional I/O mode (using SDIO as both input and output) may be enabled by writing to the SDO enable register at 00h<7> = 1. CSB (chip select bar) is an active low control that gates the read and write cycles. When CSB is high, SDO and SDIO are in a high impedance state. This pin is internally pulled down by a 30 k resistor to ground. It should not be left NC or tied low. See the General Operation of Serial Control Port section on the use of the CSB in a communication cycle.
SCLK (PIN 18) SDIO (PIN 19) SDO (PIN 20) CSB (PIN 21)
Communication Cycle--Instruction Plus Data
There are two parts to a communication cycle with the AD9510. The first writes a 16-bit instruction word into the AD9510, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9510 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer.
Write
If the instruction word is for a write operation (I15 = 0b), the second part is the transfer of data into the serial control port buffer of the AD9510. The length of the transfer (1, 2, 3 bytes, or streaming mode) is indicated by 2 bits (W1:W0) in the instruction byte. CSB can be raised after each sequence of 8 bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CSB is lowered. Stalling on nonbyte boundaries resets the serial control port. Since data is written into a serial control port buffer area, not directly into the AD9510's actual control registers, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9510, thereby causing them to take effect. This update command consists of writing to Register 5Ah<0> = 1b. This update bit is self-clearing (it is not required to write 0 to it in order to clear it). Since any number of bytes of data can be changed before issuing an
AD9510
05046-017
SERIAL CONTROL PORT
Figure 44. Serial Control Port
GENERAL OPERATION OF SERIAL CONTROL PORT
Framing a Communication Cycle with CSB
Each communications cycle (a write or a read operation) is gated by the CSB line. CSB must be brought low to initiate a communication cycle. CSB must be brought high at the completion of a communication cycle (see Figure 52). If CSB is not brought high at the end of each write or read cycle (on a byte boundary), the last byte is not loaded into the register buffer.
Rev. A | Page 42 of 60
AD9510
update command, the update simultaneously enables all register changes since any previous update. Phase offsets or divider synchronization will not become effective until a SYNC is issued (see the Single-Chip Synchronization section). Table 20. Byte Transfer Count
W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 Streaming mode
Read
If the instruction word is for a read operation (I15 = 1b), the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 4 as determined by W1:W0. The readback data is valid on the falling edge of SCLK. The default mode of the AD9510 serial control port is unidirectional mode; therefore, the requested data appears on the SDO pin. It is possible to set the AD9510 to bidirectional mode by writing the SDO enable register at 00h<7> = 1b. In bidirectional mode, the readback data appears on the SDIO pin. A readback request reads the data that is in the serial control port buffer area, not the active data in the AD9510's actual control registers.
CONTROL REGISTERS
A12:A0: These 13 bits select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. The AD9510 does not use all of the 13-bit address space. Only Bits A6:A0 are needed to cover the range of the 5Ah registers used by the AD9510. Bits A12:A7 must always be 0b. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes increment the address.
MSB/LSB FIRST TRANSFERS
The AD9510 instruction word and byte data may be MSB first or LSB first. The default for the AD9510 is MSB first. The LSB first mode may be set by writing 1b to Register 00h<6>. This takes effect immediately (since it only affects the operation of the serial control port) and does not require that an update be executed. Immediately after the LSB first bit is set, all serial control port operations are changed to LSB first order. When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from high address to low address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. When LSB_First = 1b (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. The AD9510 serial control port register address decrements from the register address just written toward 0000h for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the serial control port register address increments from the address just written toward 1FFFh for multibyte I/O operations. Unused addresses are not skipped during multibyte I/O operations; therefore, it is important to avoid multibyte I/O operations that would include these addresses.
SCLK SDIO SDO CSB SERIAL CONTROL PORT
REGISTER BUFFERS
UPDATE REGISTERS 5Ah <0>
AD9510
CORE
Figure 45. Relationship Between Serial Control Port Register Buffers and Control Registers of the AD9510
The AD9510 uses Addresses 00h to 5Ah. Although the AD9510 serial control port allows both 8-bit and 16-bit instructions, the 8-bit instruction mode provides access to five address bits (A4 to A0) only, which restricts its use to the address space 00h to 01F. The AD9510 defaults to 16-bit instruction mode on powerup. The 8-bit instruction mode (although defined for this serial control port) is not useful for the AD9510; therefore, it is not discussed further in this data sheet.
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, W1:W0, indicate the length of the transfer in bytes. The final 13 bits are the address (A12:A0) at which to begin the read or write operation. For a write, the instruction word is followed by the number of bytes of data indicated by Bits W1:W0, which is interpreted according to Table 20.
05046-018
Rev. A | Page 43 of 60
AD9510
Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB I15 R/W I14 W1 I13 W0 I12 A12 = 0 I11 A11 = 0 I10 A10 = 0 I9 A9 = 0 I8 A8 = 0 I7 A7 = 0 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
CSB SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) DATA
Figure 46. Serial Control Port Write--MSB First, 16-Bit Instruction, 2 Bytes Data
CSB SCLK DON'T CARE SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) DATA
REGISTER (N - 2) DATA
REGISTER (N - 3) DATA
DON'T CARE
Figure 47. Serial Control Port Read--MSB First, 16-Bit Instruction, 4 Bytes Data
tDS tS
CSB
tHI tDH tLO
tCLK
tH
SCLK
DON'T CARE
DON'T CARE
SDIO
Figure 48. Serial Control Port Write-MSB First, 16-Bit Instruction, Timing Measurements
CSB
SCLK
05046-022
tDV
SDIO SDO DATA BIT N DATA BIT N- 1
Figure 49. Timing Diagram for Serial Control Port Register Read
CSB SCLK DON'T CARE SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE DON'T CARE
05046-023
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N + 1) DATA
Figure 50. Serial Control Port Write--LSB First, 16-Bit Instruction, 2 Bytes Data
Rev. A | Page 44 of 60
05046-021
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
05046-020
SDO DON'T CARE
05046-019
SDIO DON'T CARE
AD9510
tS
CSB
tH
tCLK tHI
SCLK
tLO
tDS
tDH
SDIO BI N BI N + 1
05046-040
Figure 51. Serial Control Port Timing--Write
Table 22. Serial Control Port Timing
Parameter tDS tDH tCLK tS tH tHI tLO Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state
CSB TOGGLE INDICATES CYCLE COMPLETE CSB 16 INSTRUCTION BITS + 8 DATA BITS SCLK
tPWH
16 INSTRUCTION BITS + 8 DATA BITS
SDIO
COMMUNICATION CYCLE 1
COMMUNICATION CYCLE 2
05046-067
TIMING DIAGRAM FOR TWO SUCCESSIVE CUMMUNICATION CYCLES. NOTE THAT CSB MUST BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.
Figure 52. Use of CSB to Define Communications Cycle
Rev. A | Page 45 of 60
AD9510 REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 23. AD9510 Register Map
Addr (Hex) 00 Bit 0 (LSB) Def. Value (Hex) 10
Parameter Serial Control Port Configuration
Bit 7 (MSB) SDO Inactive (Bidirectional Mode)
Bit 6 LSB First
Bit 5 Soft Reset
Bit 4 Long Instruction Not Used Not Used Not Used
Bit 3
Bit 2
Bit 1 Not Used
Notes
01 02 03 PLL
04 05 06 07 08 09 0A 0B 0C 0D
A Counter B Counter B Counter PLL 1 PLL 2 PLL 3 PLL 4 R Divider R Divider PLL 5
Not Used Not Used
6-Bit A Counter <5:0> 13-Bit B Counter Bits 12:8 (MSB) <4:0> 13-Bit B Counter Bits 7:0 (LSB) <7:0>
00 00 00 00 00 00 01 00 00 00
PLL Starts in PowerDown N Divider (A) N Divider (B) N Divider (B)
OE33 FINE DELAY ADJUST 34 35 Delay Bypass 5 Delay FullScale 5 Delay Fine Adjust 5 Delay Bypass 6 Delay FullScale 6
Not Used Not Used LOR Lock_Del LOR <6:5> Enable Not Used CP Mode <1:0> PFD PLL Mux Select <5:2>Signal on STATUS Polarity pin Not Used CP Current <6:4> Not Reset R Reset N Reset All Used Counter Counter Counters Not Used Prescaler P <4:2> Power-Down <1:0> B Not Bypass Used Not Used 14-Bit R Divider Bits 13:8 (MSB) <5:0> 14-Bit R Divider Bits 13:8 (MSB) <7:0> Not Used Not Used Digital Digital Antibacklash Lock Lock Pulse Width <1:0> Det. Det. Enable Window Not Used
Not Used
N Divider (P) R Divider R Divider
Not Used Not Used Ramp Capacitor <5:3>
Bypass Ramp Current <2:0>
01 00
36 37 38 39
Not Used
5-Bit Fine Delay <5:1> Not Used Not Used
Must be 0 Bypass Ramp Current <2:0>
00 04 01 00
Fine Delays Bypassed Bypass Delay Max. Delay FullScale Min. Delay Value Bypass Delay Max. Delay FullScale
Not Used
Ramp Capacitor <5:3>
Rev. A | Page 46 of 60
AD9510
Addr (Hex) 3A 3B 3C 3D 3E 3F 40 OUTPUTS LVPECL OUT0 LVPECL OUT1 LVPECL OUT2 LVPECL OUT3 LVDS_CMOS OUT 4 LVDS_CMOS OUT 5 LVDS_CMOS OUT 6 LVDS_CMOS OUT 7 Not Used Not Used Not Used Not Used Not Used CMOS Inverted Driver On CMOS Inverted Driver On CMOS Inverted Driver On CMOS Inverted Driver On Not Used Parameter Delay Fine Adjust 6 Bit 7 (MSB) Bit 6 Not Used Bit 5 Bit 4 Bit 3 Bit 2 5-Bit Fine Delay <5:1> Not Used Power-Down <1:0> Output Level <3:2> Power-Down <1:0> Output Level <3:2> Power-Down <1:0> Output Level <3:2> Power-Down <1:0> Output Level <3:2> Logic Output Level Output Select <2:1> Power Logic Select Logic Select Logic Select Output Level <2:1> Output Level <2:1> Output Level <2:1> Output Power Output Power Output Power Bit 1 Bit 0 (LSB) Not Used Def. Value (Hex) 00 04 0A 08 08 08 02 OFF ON ON ON LVDS, ON Notes Min. Delay Value
41
Not Used
02
LVDS, ON
42
Not Used
03
LVDS, OFF
43
Not Used
03
LVDS, OFF
44 CLK1 AND CLK2 Clocks Select, Power-Down (PD) Options
45
Not Used
CLKs in PD
REFIN PD
CLK to PLL PD
CLK2 PD
CLK1 PD
Select CLK IN
01
Input Receivers All Clocks ON, Select CLK1
46, 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 DIVIDERS Divider 0 Divider 0 Divider 1 Divider 1 Divider 2 Divider 2 Divider 3 Divider 3 Divider 4 Divider 4 Divider 5 Divider 5 Divider 6 Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4>
Not Used High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> 00 00 00 00 11 00 33 00 00 00 11 00 00 Divide by 2 Phase = 0 Divide by 2 Phase = 0 Divide by 4 Phase = 0 Divide by 8 Phase = 0 Divide by 2 Phase = 0 Divide by 4 Phase = 0 Divide by 2
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Rev. A | Page 47 of 60
AD9510
Addr (Hex) 55 56 57 Parameter Divider 6 Divider 7 Divider 7 FUNCTION FUNCTION Pin and Sync Bit 7 (MSB) Bypass Bit 6 Bit 5 Force No Sync Low Cycles <7:4> Force No Sync Set FUNCTION Pin Bit 4 Start H/L Bit 3 Bit 2 Bit 1 Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> Bit 0 (LSB) Def. Value (Hex) 00 00 00 Notes Phase = 0 Divide by 2 Phase = 0
Bypass
Start H/L
58
Not Used
PD Sync
PD All Ref.
Sync Reg.
Sync Select
Sync Enable
00
FUNCTION Pin = RESETB SelfClearing Bit
59 5A
Update Registers END
Not Used Not Used
Update Registers
00
Rev. A | Page 48 of 60
AD9510
REGISTER MAP DESCRIPTION
Table 24 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23. Table 24. AD9510 Register Descriptions
Reg. Addr. (Hex) Bit(s) Name Serial Control Port Configuration 00 <3:0> 00 00 <4> <5> Long Instruction Soft Reset
Description Any changes to this register takes effect immediately. Register 5Ah<0> Update Registers does not have to be written. Not Used. When this bit is set (1), the instruction phase is 16 bits. When clear (0), the instruction phase is 8 bits. The default, and only, mode for this part is long instruction (Default = 1b). When this bit is set (1), the chip executes a soft reset, restoring default values to the internal registers, except for this register, 00h. This bit is not self-clearing. A clear (0) has to be written to it in order to clear it. When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register addressing increments. If this bit is clear (0), data is oriented as MSB first and register addressing decrements. (Default = 0b, MSB first.) When set (1), the SDO pin is tri-state and all read data goes to the SDIO pin. When clear (0), the SDO is active (unidirectional mode). (Default = 0b.)
00
<6>
LSB First
00
<7>
SDO Inactive (Bidirectional Mode) Not Used
01 02 03 04 04 05 05 06 07 07 07 07
<7:0> <7:0> <7:0> PLL Settings <5:0> <7:6> <4:0> <7:5> <7:0> <1:0> <2> <4:3> <6:5> A Counter B Counter MSBs B Counter LSBs LOR Enable LOR Initial Lock Detect Delay
Not Used Not Used Not Used 6-Bit A Counter <5:0> Not Used 13-Bit B Counter (MSB) <12:8> Not Used 13-Bit B Counter (LSB) <7:0> Not Used 1 = Enables the Loss-of-Reference (LOR) Function; (Default = 0b) Not Used LOR Initial Lock Detect Delay. Once a lock detect is indicated, this is the number of phase frequency detector (PFD) cycles that occur prior to turning on the LOR monitor. <6> <5> LOR Initial Lock Detect Delay 0 0 3 PFD Cycles (Default) 0 1 6 PFD Cycles 1 0 12 PFD Cycles 1 1 24 PFD Cycles Not Used
07 08
<7> <1:0> Charge Pump Mode
<1> 0 0 1 1
<0> 0 1 0 1
Charge Pump Mode Tri-Stated (Default) Pump-Up Pump-Down Normal Operation
Rev. A | Page 49 of 60
AD9510
Reg. Addr. (Hex) Bit(s) Name 08 <5:2> PLL Mux Control Description <5> <4> <3> <2> MUXOUT--Signal on STATUS Pin 0 0 0 0 Off (Signal Goes Low) (Default) 0 0 0 1 Digital Lock Detect (Active High) 0 0 1 0 N Divider Output 0 0 1 1 Digital Lock Detect (Active Low) 0 1 0 0 R Divider Output 0 1 0 1 Analog Lock Detect (N Channel, Open-Drain) 0 1 1 0 A Counter Output 0 1 1 1 Prescaler Output (NCLK) 1 0 0 0 PFD Up Pulse 1 0 0 1 PFD Down Pulse 1 0 1 0 Loss-of-Reference (Active High) 1 0 1 1 Tri-State 1 1 0 0 Analog Lock Detect (P Channel, Open-Drain) 1 1 0 1 Loss-of-Reference or Loss-of-Lock (Inverse of DLD) (Active High) 1 1 1 0 Loss-of-Reference or Loss-of-Lock (Inverse of DLD) (Active Low) 1 1 1 1 Loss-of-Reference (Active Low) MUXOUT is the PLL portion of the STATUS output MUX 0 = Negative (Default), 1 = Positive
08
<6>
Phase-Frequency Detector (PFD) Polarity
08 09 09 09 09 09
<7> <0> <1> <2> <3> <6:4>
09 0A
Not Used Reset All Counters 0 = Normal (Default), 1 = Reset R, A, and B Counters N-Counter Reset 0 = Normal (Default), 1 = Reset A and B Counters R-Counter Reset 0 = Normal (Default), 1 = Reset R Counter Not Used Charge Pump (CP) Current Setting <6> <5> <4> ICP (mA) 0 0 0 0.60 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 Default = 000b These currents assume: CPRSET = 5.1 k Actual current can be calculated by: CP_lsb = 3.06/CPRSET <7> Not Used <1:0> PLL Power-Down 01 = Asynchronous Power-Down (Default) <1> <0> Mode 0 0 Normal Operation 0 1 Asynchronous Power-Down 1 0 Normal Operation 1 1 Synchronous Power-Down
Rev. A | Page 50 of 60
AD9510
Reg. Addr. (Hex) Bit(s) Name 0A <4:2> Prescaler Value (P/P+1) Description
0A 0A 0A 0B 0C 0D
<5> <6>
B Counter Bypass
<4> <3> <2> Mode Prescaler Mode 0 0 0 FD Divide by 1 0 0 1 FD Divide by 2 0 1 0 DM 2/3 0 1 1 DM 4/5 1 0 0 DM 8/9 1 0 1 DM 16/17 1 1 0 DM 32/33 1 1 1 FD Divide by 3 DM = Dual Modulus, FD = Fixed Divide. Not Used Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is divided by 1. This allows the prescaler setting to determine the divide for the N divider.
0D 0D
<7> Not Used <5:0> 14-Bit Reference R Divider (MSB) <13:8> Counter, MSBs <7:0> 14-Bit Reference R Divider (MSB) <7:0> Counter, R LSBs <1:0> Antibacklash Pulse Width <1> <0> Antibacklash Pulse Width (ns) 0 0 1.3 (Default) 0 1 2.9 1 0 6.0 1 1 1.3 <4:2> Not Used <5> Digital Lock Detect Window <5> Digital Lock Detect Window (ns) Digital Lock Detect Loss-of-Lock Threshold (ns)
0 (Default) 9.5 15 1 3.5 7 Digital Lock Detect If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window Window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. 0D <6> Lock Detect 0 = Normal Lock Detect Operation (Default) Disable 1 = Disable Lock Detect 0D <7> Not Used Unused 0E-33 Not Used Fine Delay Adjust <0> Delay Control Delay Block Control Bit 34 OUT5 Bypasses Delay Block and Powers It Down (Default = 1b) (38) (OUT6) 34 <7:1> Not Used (38) <2:0> Ramp Current 35 OUT5 The slowest ramp (200 A) sets the longest full scale of approximately 10 ns.
Rev. A | Page 51 of 60
AD9510
Reg. Addr. (Hex) Bit(s) Name (39) (OUT6) Description <2> <1> <0> 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Selects the Number of Capacitors in Ramp Generation Circuit More Capacitors => Slower Ramp <5> 0 0 0 0 1 1 1 1 36 (3A) 3C <5:1> Delay Fine Adjust OUT5 (OUT6) <1:0> Power-Down LVPECL Mode (3D) (3E) (3F) OUT0 (OUT1) (OUT2) (OUT3) ON PD1 PD2 0 0 1 0 1 0 Normal Operation Test Only--Do Not Use Safe Power-Down Partial Power-Down; Use If Output Has Load Resistors Total Power-Down Use Only If Output Has No Load Resistors ON OFF OFF <1> <0> Description Output <4> 0 0 1 1 0 0 1 1 <3> 0 1 0 1 0 1 0 1 Ramp Current (A) 200 400 600 800 1000 1200 1400 1600
35 (39)
<5:3> Ramp Capacitor OUT5 (OUT6)
Number of Capacitors 4 (Default) 3 3 2 3 2 2 1
Sets Delay Within Full Scale of the Ramp; There are 32 Steps 00000 => Zero Delay (Default) 11111 => Maximum Delay
PD3
1
1
OFF
3C (3D) (3E)
<3:2> Output Level LVPECL OUT0 (OUT1)
Output Single-Ended Voltage Levels for LVPECL Outputs
Rev. A | Page 52 of 60
AD9510
Reg. Addr. (Hex) Bit(s) Name (3F) (OUT2) (OUT3) Description
3C (3D) (3E) (3F) 40
<7:4>
<3> 0 0 1 1 Not Used
<2> 0 1 0 1
Output Voltage (mV) 500 340 810 (Default) 660
<0>
Power-Down
Power-Down Bit for Both Output and LVDS Driver 0 = LVDS/CMOS on (Default) 1 = LVDS/CMOS Power-Down
(41) (42) (43)
40 (41) (42) (43)
LVDS/CMOS OUT4 (OUT5) (OUT6) (OUT7) <2:1> Output Current Level LVDS OUT4 (OUT5) (OUT6) (OUT7) <2> 0 0 1 1 <1> 0 1 0 1 Current (mA) 1.75 3.5 (Default) 5.25 7 Termination () 100 100 50 50
40 (41) (42) (43)
40 (41) (42) (43) 40 (41) (42) (43) 44
LVDS/CMOS Select 0 = LVDS (Default) 1 = CMOS OUT4 (OUT5) (OUT6) (OUT7) <4> Inverted CMOS Effects Output Only when in CMOS Mode Driver 0 = Disable Inverted CMOS Driver (Default) 1 = Enable Inverted CMOS Driver OUT4 (OUT5) (OUT6) (OUT7) <7:5> Not Used
<3>
<7:0>
Not Used
Rev. A | Page 53 of 60
AD9510
Reg. Addr. (Hex) Bit(s) Name 45 <0> Clock Select 45 45 45 45 45 45 46 47 48 (4A) (4C) (4E) (50) (52) (54) (56) <7:4> 48 (4A) (4C) (4E) (50) (52) (54) (56) <3:0> 49 (4B) (4D) (4F) (51) (53) (55) (57) <4> 49 (4B) (4D) (4F) (51) (53) (55) (57) <1> <2> <3> <4> <5> <7:6> <7:0> <7:0> <3:0> Description 0: CLK2 Drives Distribution Section 1: CLK1 Drives Distribution Section (Default) CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b) CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b) 1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b) Prescaler Clock Power-Down REFIN Power-Down 1 = Power-Down REFIN (Default = 0b) All Clock Inputs 1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree; Power-Down (Default = 0b) Not Used Not Used Not Used Divider High Number of Clock Cycles Divider Output Stays High OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Divider Low Number of Clock Cycles Divider Output Stays Low OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Phase Offset Phase Offset (Default = 0000b) OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Start Selects Start High or Start Low (Default = 0b) OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7)
Rev. A | Page 54 of 60
AD9510
Reg. Addr. (Hex) Bit(s) Name <5> Force 49 (4B) (4D) (4F) (51) (53) (55) (57) <6> 49 (4B) (4D) (4F) (51) (53) (55) (57) <7> 49 (4B) (4D) (4F) (51) (53) (55) (57) 58 58 58 Description Forces Individual Outputs to the State Specified in Start (Above) This Function Requires That Nosync (Below) Also Be Set (Default = 0b)
<0> <1> <2>
OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Nosync Ignore Chip-Level Sync Signal (Default = 0b) OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Bypass Divider Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b) OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) SYNC Detect Enable 1 = Enable SYNC Detect (Default = 0b) SYNC Select Soft SYNC 1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles 0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit's polarity is reversed. That is, a high level forces selected outputs into a known state, and a high > low transition triggers a sync (default = 0b). 1 = Power-Down the References for the Distribution Section (Default = 0b)
58 58 58
<3> <4>
Dist Ref PowerDown SYNC Power-Down 1 = Power-Down the SYNC (Default = 0b)
<6:5> FUNCTION Pin Select <6> <5> Function 0 0 RESETB (Default) 0 1 SYNCB 1 0 Test Only; Do Not Use 1 1 PDB Not Used Not Used A 1 written to this bit updates all registers and transfers all serial control port register buffer contents to the control registers on the next rising SCLK edge. This is a self-clearing bit; a 0 does not have to be written to clear it. Not Used
58 59 5A
<7> <7:0> <0> Update Registers
5A END
<7:1>
Rev. A | Page 55 of 60
AD9510 POWER SUPPLY
The AD9510 requires a 3.3 V 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9510 with the power supply voltage within this range. The absolute maximum range of -0.3 V - +3.6 V, with respect to GND, must never be exceeded on the VS pin. Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 F). The AD9510 should be bypassed with adequate capacitors (0.1 F) at all power pins as close as possible to the part. The layout of the AD9510 evaluation board (AD9510/PCB or AD9510-VCO/PCB) is a good example. The AD9510 is a complex part that is programmed for its desired operating configuration by on-chip registers. These registers are not maintained over a shutdown of external power. This means that the registers can loose their programmed values if VS is lost long enough for the internal voltages to collapse. Careful bypassing should protect the part from memory loss under normal conditions. Nonetheless, it is important that the VS power supply not become intermittent, or the AD9510 risks losing its programming. The internal bias currents of the AD9510 are set by the RSET and CPRSET resistors. These resistors should be as close as possible to the values given as conditions in the Specifications section (RSET = 4.12 k and CPRSET = 5.1 k). These values are standard 1% resistor values, and should be readily obtainable. The bias currents set by these resistors determine the logic levels and operating conditions of the internal blocks of the AD9510. The performance figures given in the Specifications section assume that these resistor values are used. The VCP pin is the supply pin for the charge pump (CP). The voltage at this pin (VCP) may be from VS up to 5.5 V, as required to match the tuning voltage range of a specific VCO/VCXO. This voltage must never exceed the absolute maximum of 6 V. VCP should also never be allowed to be less than -0.3 V below VS or GND, whichever is lower. The exposed metal paddle on the AD9510 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9510; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB. See the layout of the AD9510 evaluation board (AD9510/PCB or AD9510-VCO/PCB) for a good example.
POWER MANAGEMENT
The power usage of the AD9510 can be managed to use only the power required for the functions that are being used. Unused features and circuitry can be powered down to save power. The following circuit blocks can be powered down, or are powered down when not selected (see the Register Map and Description section): * The PLL section can be powered down if not needed. * Any of the dividers are powered down when bypassed-- equivalent to divide-by-one. * The adjustable delay blocks on OUT5 and OUT6 are powered down when not selected. * Any output may be powered down. However, LVPECL outputs have both a safe and an off condition. When the LVPECL output is terminated, only the safe shutdown should be used to protect the LVPECL output devices. This still consumes some power. * The entire distribution section can be powered down when not needed. Powering down a functional block does not cause the programming information for that block (in the registers) to be lost. This means that blocks can be powered on and off without otherwise having to reprogram the AD9510. However, synchronization is lost. A SYNC must be issued to resynchronize (see the Single-Chip Synchronization section).
Rev. A | Page 56 of 60
AD9510 APPLICATIONS
USING THE AD9510 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by
1 SNR = 20 x log 2ftj
level, termination) should be considered when selecting the best clocking/converter solution.
CMOS CLOCK DISTRIBUTION
The AD9510 provides four clock outputs (OUT4 to OUT7), which are selectable as either CMOS or LVDS levels. When selected as CMOS, these outputs provide for driving devices requiring CMOS level logic at their clock inputs. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be followed. Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity.
10 CMOS MICROSTRIP
05046-025
where f is the highest analog frequency being digitized, and tj is the rms jitter on the sampling clock. Figure 53 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB).
tj = 50fs 120 tj = 0.1ps 100 tj = 1ps
SNR (dB)
SNR = 20log10
1 2ftj 18 16 14 12 10
ENOB
60.4 1.0 INCH
5pF GND
80 tj = 10ps 60 tj = 100ps 40
Figure 54. Series Termination of CMOS Output
8 6 4
05046-024
tj = 1ns
20 1 3 10 30 100 FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
Figure 53. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 on the ADI website at www.analog.com. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection, which can provide superior clock performance in a noisy environment.) The AD9510 features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9510 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 55. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VPULLUP = 3.3V 50 100 3pF
05046-027
10 CMOS
OUT4, OUT5, OUT6, OUT7 SELECTED AS CMOS
100
Figure 55. CMOS Output with Far-End Termination
Rev. A | Page 57 of 60
AD9510
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9510 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second differential output option for the AD9510. LVDS uses a current mode output stage with several user-selectable current levels. The normal value (default) for this current is 3.5 mA, which yields 350 mV output swing across a 100 resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 58.
3.3V 3.3V
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL) outputs of the AD9510 provide the lowest jitter clock signals available from the AD9510. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. A simplified equivalent circuit in Figure 41 shows the LVPECL output stage. In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 56. The resistor network is designed to match the transmission line impedance (50 ) and the desired switching threshold (1.3 V).
3.3V 3.3V 50 SINGLE-ENDED (NOT COUPLED) 50
05046-030
LVDS
100 100 DIFFERENTIAL (COUPLED)
LVDS
Figure 58. LVDS Output Termination
127
127
3.3V
See Application Note AN-586 on the ADI website at www.analog.com for more information on LVDS.
LVPECL
LVPECL
POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION
Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance.
VT = VCC - 1.3V
83
83
Figure 56. LVPECL Far-End Termination
3.3V 0.1nF DIFFERENTIAL (COUPLED)
3.3V
LVPECL
0.1nF 200
100
LVPECL
Figure 57. LVPECL with Parallel Transmission Line
05046-031
200
Rev. A | Page 58 of 60
05046-032
AD9510 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
*4.85 4.70 SQ 4.55
0.45 0.40 0.35
33 32
16 17
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
7.50 REF
SEATING PLANE
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION
Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm x 9 mm Body (CP-64-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9510BCPZ 1 AD9510BCPZ-REEL71 AD9510/PCB AD9510-VCO/PCB
1
Temperature Range -40C to +85C -40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP) 64-Lead Lead Frame Chip Scale Package (LFCSP) Evaluation Board Without VCO or VCXO or Loop Filter Evaluation Board With 245.76 MHz VCXO, Loop Filter
Package Option CP-64-1 CP-64-1
Z = Pb-free part.
Rev. A | Page 59 of 60
AD9510 NOTES
(c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05046-0-5/05(A)
Rev. A | Page 60 of 60

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